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Template Revision 2.0 - on construction

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL): for example:https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0703/

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Table of Contents

Table of Contents

Overview

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Notes :

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Refer to

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links:

- https://wiki.trenz-electronic.de/display/

PD/TE0714+TRM for the online version of this manual and the rest of available documentation.

- CON/Redirects

The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. TE0714 is the smallest module with transceiver (3 x 4 cm).

Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

List of key features of the PCB

Xilinx Artix-7 FPGA (A15T, A35T, A50T)
Rugged for shock and high vibration
16 MByte QSPI Flash memory
Differential MEMS oscillator for MGT clocking
MEMS oscillator for PL clocks (Optional)
Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
- 144 FPGA I/O's (Max 68 differential)
- XADC analog input
- 4 GTP (high-performance transceiver) lanes
- GT reference clock inputs
- Optimized I/O and power pins for good signal integrity
On-board high-efficiency DC-DC converters
Power supply for all on-board components
eFUSE bit-stream encryption (AES)
One user configurable LED

...

FPGA Type (A15T, A35T, A50T), temperature grade
GT clock frequency (or none if not implemented)
PL clock frequency and precision (or none if not implemented)
Config and B14 bank Voltage: 1.8V or 3.3V
SPI Flash type (or none if not implemented)
LED Color (or none if not implemented)
PUDC Pin strapping (pull high or pull down)
GT power enable pin strapping (default power enabled or disabled)

Block Diagram

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Main Components

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Main Components

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Picture of the PCB (top and bottom side) with labels of important components
Add List below

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Xilinx Artix-7 FPGA (XC7A series), U4
16 MByte SPI Flash, U7
B2B connector Samtec Razor Beam™ LSHM-150, JM2
B2B connector Samtec Razor Beam™ LSHM-150, JM1
25 MHz oscillator, U8
Single output low-dropout linear regulator (1.2V_MGT), U6
Single output low-dropout linear regulator (1.0V_MGT), U5
Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
Red indication LED, D4
Step-down DC-DC converter (1.0V), U1
PFET load switch with configurable slew rate (3.3V), Q1
Low-power step-down DC-DC converter (1.8V), U3
Voltage detector for circuit initialization and timing supervision, U23

Initial Delivery State

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Storage device name	Content	Notes
SPI Flash OTP Area	Empty, not programmed	Except serial number programmed by flash vendor
SPI Flash Quad Enable bit	Programmed
SPI Flash main array	demo design
eFUSE USER	Not programmed
eFUSE Security	Not programmed

Control Signals

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Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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MGT_AVCC

MGT_AVTT

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Overview of Boot Mode, Reset, Enables,
Boot process is controlled by signals on the board to board (B2B) connector.
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Signal Direction
Signal State
Description
BOOTMODE

input
high or open
Master SPI, x4 Mode
low or ground
Slave SelectMAP
PROG_B input pulsed low Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge).
DONE output high Completion of configuration sequence.
Note
SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.

Signals, Interfaces and Pins

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Notes :

For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...

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JTAG Interface

JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.

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Signal Name	B2B Pin
TCK	JM1:89
TDI	JM1:85
TDO	JM1:87
TMS	JM1:91

On-board LED's

There is one LED on TE0714 module:

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LED	Color	FPGA	Notes
D4	Red	K18

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Clock

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Clock	Default Frequency	IC	FPGA	Notes
CLK25MHz	25 MHz	U8	T14	Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank.
MGT_CLK	125MHz	U2	B6/B5	Frequency depends on the module variant

Boot Process

Boot mode is controlled by the MODE signal on the board to board (B2B) connector:

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MODE signal State

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Boot Mode

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high or open

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Master SPI, x4 Mode

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low or ground

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Slave SelectMAP

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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FPGA Bank	B2B Connector	I/O Signal Count	Voltage Level	Notes
14	JM1	6	VCCIO_0
14	JM2	36	VCCIO_0	NB! 17 LVDS pairs possible.
15	JM2	48	VCCIO15	Supplied by the baseboard.
34	JM1	48	VCCIO34	Supplied by the baseboard.
216	JM1	16	MGT_AVCC MGT_AVTT	4 x GTP lanes.

Please refer to the Pin-out tables page for additional information.

On-board Peripherals

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Notes :

add subsection for every component which is important for design, for example:
- Ethernet PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

Note
SPI D2 and D3 have no pull-ups on the module so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.

On-board Peripherals

16 MByte Quad SPI Flash

On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

...

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

TE0714 needs one single power supply with nominal of 3.3V.

Power Consumption

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Test Condition (25 °C ambient)	VIN Current mA	Notes
TE0714-35, TEBT0714, empty design, GT not enabled	110mA

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

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Power-On Sequence

There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.

Bank Voltages

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Bank	Voltage	Notes
0 Config and B14	1.8V or 3.3V	Depends on module variant
15	User	Supplied from baseboard via B2B connector, max 3.3V
34	User	Supplied from baseboard via B2B connector, max 3.3V

Board to Board Connectors

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Variants Currently In Production

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FPGA Chip Model

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B14/Config Voltage [V]

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors
Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

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Note
On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module.

Technical Specifications

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Parameter	Min	Max	Units

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Reference Document
VIN supply voltage	-0.1	6.0	V	-
HR I/O banks supply voltage (VCCO)	-0.5	3.6	V	Xilinx datasheet DS181
HR I/O banks input voltage	-0.4	VCCO + 0.55	V	Xilinx datasheet DS181
GTP transceivers Tx/Rx input voltage	-0.5	1.26	V	Xilinx datasheet DS181
Voltage on module JTAG pins	-0.4	VCCO_0 + 0.55	V	Xilinx datasheet DS181
Storage temperature	-40	+85	°C	-

Recommended Operating Conditions

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Parameter	Min	Max	Units

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Reference Document
VIN supply voltage	3.135	3.45	V	-
HR I/O banks supply voltage (VCCO)	1.14	3.465	V	Xilinx datasheet DS181
HR I/O banks input voltage	-0.20	VCCO + 0.20	V	Xilinx datasheet DS181
Voltage on module JTAG pins	3.135	3.465	V	Xilinx datasheet DS181

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Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

...

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Note
Please check Xilinx datasheet DS181 for complete list of absolute maximum and recommended operating ratings for the Artix-7.

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Physical Dimensions

Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.

All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.

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Weight

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Variant	Weight in g	Note
2IC6	8.3	Plain Module

Variants Currently In Production

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Set correct link to the shop page overview table of the product on English and German, if not available, set
- https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/
- https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/

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Trenz shop TE0714 overview page
English page	German page

Note
On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module.

Revision History

Hardware Revision History

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Date	Revision

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Note	PCN

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	Documentation Link
2018-11-01	02	Replaced SPI Flash		TE0714-02
2016-08-04	02	VCCIO0 added to B2B	PCN-20160815	TE0714-02
	01	-	-	TE0714-01

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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Date

Revision

Authors

Description

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infoType	Create date
dateFormat	yyyy-MM-dd
type	Flat
showVersions	false

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infoType	Current version
prefix	v.
type	Flat
showVersions	false

Page info

infoType	Modified by
type	Flat
showVersions	false

Update to TRM version 2.0 with DrawIO Figures
Added Figure Power Distribution

2018-04-04

v.35

Martin Rohrmüller

Corrected clock net designator in table.

2017-05-28

V.27

Jan Kumann

Board-to-Board I/O section added.

New physical dimensions images.

Documents sections rearranged.

2017-03-20

V.26

John Hartfiel

Notes on Clocking section.

2017-01-27

v.25

Jan Kumann

New block diagram.

2016-12-01

v.17

Jan Kumann

Changes in the document structure, few corrections.

2016-11-18

v.14

Thorsten Trenz, Emmanuel Vassilakis

Hardware revision 02 specific changes.

2016-06-01

v.9

Antti Lukats

Initial version.

...

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 35

New Version 36

Key

Overview

Key Features

Block Diagram

Main Components

Scroll TitleanchorFigure_1titleFigure 1: TE0714 block diagram Scroll Ignore draw.io DiagrambordertrueviewerToolbartruefitWindowfalsediagramNameBD-TE0714-02simpleViewerfalsewidthdiagramWidth641revision4 Scroll OnlyImage Added

Main Components

Initial Delivery State

Control Signals

Board to Board (B2B) I/Os

Signals, Interfaces and Pins

JTAG Interface

On-board LED's

Clock

Boot Process

Board to Board (B2B) I/Os

On-board Peripherals

On-board Peripherals

16 MByte Quad SPI Flash

Power Supply

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Bank Voltages

Board to Board Connectors

Variants Currently In Production

Page propertieshiddentrueidCommentsThis section is optional and only for modules.use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors Include Page4 x 5 SoM LSHM B2B Connectors4 x 5 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

Technical Specifications

Recommended Operating Conditions

Operating Temperature Ranges

Physical Dimensions

Weight

Variants Currently In Production

Revision History

Hardware Revision History

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors
Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B Connectors