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Scroll Title
anchorTable_LEDs
titleTable 4: LED connetionconnection.

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LED

Color

FPGA

Notes

D4

Red

K18

User programmable

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Scroll Title
anchorTable_Clocks
titleTable 5: Clock signals.

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Clock

Default Frequency

IC

FPGA

Notes

CLK25MHz

25 MHz

U8

T14

Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank.
MGT_CLK

125MHz

U2

B6/B5

Frequency depends on the module variant

Board to Board (B2B) I/Os

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Page properties
hiddentrue
idComments
  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

Include Page
3 x 4 x 5 SoM LSHM B2B Connectors
3 x 4 x 5 SoM LSHM B2B Connectors

Technical Specifications

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anchorTable_Document_Change_History
titleTable 14: Document change history

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Date

Revision

Authors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
prefixv.
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Page info
infoTypeModified by
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  • Updated to TRM version 2.1
  • Updated B2B Connectors
  • Style modifications

2018-09-17
V.38
Martin Rohrmüller
  • Added power rail section
  • Added Rev 02 Flash PCN
  • corrected Corrected table headings
2018-09-17v.36Martin Rohrmüller

  • Update to TRM version 2.0 with DrawIO Figures

  • Added Figure Power Distribution
2018-04-04

v.35

Martin RohrmüllerCorrected clock net designator in table.
2017-05-28
V.27
Jan Kumann

Board-to-Board I/O section added.

New physical dimensions images.

Documents sections rearranged.

2017-03-20

V.26

John HartfielNotes on Clocking section.
2017-01-27v.25Jan KumannNew block diagram.
2016-12-01

v.17

Jan KumannChanges in the document structure, few corrections.
2016-11-18
v.14

Thorsten Trenz, Emmanuel Vassilakis

Hardware revision 02 specific changes.

2016-06-01

v.9

Antti Lukats

Initial version.

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