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Control Signals
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- Overview of Boot Mode, Reset, Enables,
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Boot process is controlled by signals on the board to board (B2B) connector.
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| anchor | Table_Boot_Signals |
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| title | Table 2: Boot signals. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| Signal | Direction | Signal State | Description |
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BOOTMODE
| input | high or open | Master SPI, x4 Mode
| low or ground
| Slave SelectMAP | | PROG_B | input | pulsed low | Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge). | | DONE | output | high | Completion of configuration sequence. |
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| Note |
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SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
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| Scroll Title |
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| anchor | Table_Clocks |
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| title | Table 5: Clock signals. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | 12%14%,12%14%,8%6%,10%9%,58%57% |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Clock | Default Frequency | IC | FPGA | Notes |
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| CLK25MHz | 25 MHz | U8 | T14 | Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank. | | MGT_CLK | 125MHz | U2 | B6/B5 | Frequency depends on the module variant |
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