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The TEC0850 board is equipped with 3 CompactPCI high-speed backplane connectors which provide serial high-speed interconnects with transmission rates up to 12 Gb/s to the Zynq MPSoCs MGT lanes. On the cPCI connectors are also available single-ended Zynq MPSoC PL HP I/O's, high-speed USB 2.0 interface , and single-ended FPGA I/O pins Zynq MPSoC and 's of the System Controller FPGA.
The connectors support single-ended and differential signaling as to the Zynq MPSoC PL HP banks 65 and 66 as those FPGA I/O's are routed from the FPGA banks as LVDS-pairs to the backplane connector.
The TEC0850 board is designed to be connected to the System Slot of the backplane connector, whereby 4 of the 6 connectors of the System Slot configuration are fitted to the TEC0850 board.
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| Scroll Title |
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| anchor | Table_default_mio |
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| title | Table 13: Default MIO Configuration |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| PS MIO | Function | Connected to |
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| 0 | QSPI* | U24-B2, CLK |
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| 1 | QSPI* | U24-D2, DO/IO1
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| 2 | QSPI* | U24-C4, WP/IO2
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| 3 | QSPI* | U24-D4, HOLD/IO3 |
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| 4 | QSPI* | U24-D3, DI/IO0 |
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| 5 | QSPI* | U24-C2, CS |
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| 6 | - | not connected |
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| 7 | QSPI* | U25-C2, CS |
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| 8 | QSPI* | U25-D3, DI/IO0 |
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| 9 | QSPI* | U25-D2, DO/IO1 |
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| 10 | QSPI* | U17-C4, WP/IO2 |
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| 11 | QSPI* | U25-D4, HOLD/IO3 |
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| 12 | QSPI* | U25-B2, CLK |
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| 13 ... 15 | - | not connected |
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| 16 | USB2 PHY Reset | USB2 PHY U11, pin27 |
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| 17 | USB2 PHY Reset | USB2 PHY U13, pin27 (def. not solderedoptional, PHY not fitted by default) |
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| 18 ... 19 | - | not connected |
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| 20 ...21 | PS MIO I²C | I²C peripherals |
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| 22 ... 25 | user MIO | SC FPGA U18, bank 2 |
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| 26 ... 38 | RGMII | GbE PHY U20 |
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| 39 ... 44 | - | not connected |
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| 45 ... 51 | SD IO | MicroSD Card socket J11 |
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| 52 ... 63 | USB2 ULPI | USB2 PHY U11 |
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| 64 ... 75 | USB2 ULPI | USB2 PHY U13 (def. not solderedoptional, PHY not fitted by default) |
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| 76 ... 77 | ETH MDC / MDIO | GbE PHY U20 |
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* Flash is used as QSPI dual parallel |
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USB2 PHY U11 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U12. There is also the option to equip the TEC0850 board with a second USB2 PHY U13 connected to the optional cPCI backplane connector J3. Both, the optional USB2 PHY U13 and cPCI connector J3 are not fitted by default.
| Scroll Title |
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| anchor | Figure_usb2_phy |
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| title | Figure 20: TEC0850 cPCI USB2 interface |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 12 |
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| diagramName | TEC0850 USB2 PHY |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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| Scroll Title |
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| anchor | Table_usb2_phy_io |
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| title | Table 22: USB2 ULPI interface description |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| USB2 PHY U11 Pin | Connected to | Notes |
|---|
| ULPI | PS bank MIO52 ... MIO63 | Zynq Ultrascale+ USB0 MIO pins are connected to the PHY | | REFCLK | - | 52MHz from onboard oscillator U12 | | REFSEL[0..2] | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz) | | RESETB | Zynq MPSoC MIO16, pin AM16 | Low active USB2 PHY Reset
| | DP, DM | cPCI connector J1 | USB2 data lane | | CPEN | - | External USB power switch active-high enable signal | | VBUS | 5V | Connected to USB VBUS onboard 5V voltage level via a series of resistors, see schematic | | ID | 3.3V | B-device |
|
Gigabit Ethernet PHY
| optional USB2 PHY U13 Pin | Connected to | Notes |
|---|
| ULPI | PS bank MIO64 ... MIO75 | Zynq Ultrascale+ USB1 MIO pins are connected to the PHY | | REFCLK | - | 52MHz from onboard oscillator U12 | | REFSEL[0..2] | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz) | | RESETB | Zynq MPSoC MIO17, pin AP16 | Low active USB2 PHY Reset | | DP, DM | optional cPCI connector J3 | USB2 data lane | | CPEN | - | External USB power switch active-high enable signal | | VBUS | 5V | Connected to onboard 5V voltage level via a series of resistors, see schematic | | ID | 3.3V | B-device |
|
Gigabit Ethernet PHY
Onboard Gigabit Ethernet PHY U20 is provided Onboard Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21.
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| Scroll Title |
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| anchor | Table_Document_Change_History |
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| title | Table 34: Document change history |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Constributor | Description |
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| Create | Modified date | | dateFormat | yyyy-MM-dd |
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| type | Flat |
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| showVersions | false | | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
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| showVersions | false |
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|
| | Page info |
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| infoType | Modified by |
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| type | Flat |
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| showVersions | false |
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|
| - added information about the option
of second USB2 PHY (not fitted by default)
|
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2018-09-19 | | | | | 29 Aug | v.93 | Ali Naseri , Oleksandr Kiyenko , John Hartfiel | | | -- | all | | Page info |
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| infoType | Modified users |
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| type | Flat |
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| showVersions | false |
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|
| |
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| Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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|
QSPI* John Hartfiel