| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | 14%,15%,5%6%,9%,57%56% |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Clock | Default Frequency | IC | FPGA | Notes |
|---|
| CLK25MHz | 25 MHz | U8 | T14 | Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank. | | MGT_CLK | 125MHz | U2 | B6/B5 | Frequency depends on the module variant |
|