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Template Revision 2.0 - on construction2

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"

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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_xanchorname
        titleFigure x: Text
        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use

        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      • Table template:

        • Layout macro can be use for landscape of large tables
      • Scroll Title
        anchorTable_x
        titleTable x: Text

        Scroll Table Layout
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        ExampleComment
        12
  • ...
      • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

        • <type>_<main section>_<name>

          • type: Figure, Table
          • main section:
            • "OV" for Overview
            • "SIP" for Signal Interfaces and Pins,
            • "OBP" for On board Peripherals,
            • "PWR" for Power and Power-On Sequence,
            • "B2B" for Board to Board Connector,
            • "TS" for Technical Specification
            • "VCP" for Variants Currently in Production
            •  "RH" for Revision History
          • name: custom, some fix names, see below
        • Fix names:
          • "Figure_OV_BD" for Block Diagram

          • "Figure_OV_MC" for Main Components

          • "Table_OV_IDS" for Initial Delivery State

          • "Table_PWR_PC" for Power Consumption

          • "Figure_PWR_PD" for Power Distribution
          • "Figure_PWR_PS" for Power Sequence
          • "Figure_PWR_PM" for Power Monitoring
          • "Table_PWR_PR" for Power Rails
          • "Table_PWR_BV" for Bank Voltages
          • "Table_TS_AMR" for Absolute_Maximum_Ratings

          • "Table_TS_ROC" for Recommended_Operating_Conditions

          • "Figure_TS_PD" for Physical_Dimensions
          • "Table_VCP_SO" for TE_Shop_Overview
          • "Table_RH_HRH" for Hardware_Revision_History

          • "Table_RH_DCH" for Document_Change_History
      • Use Anchor in the document: add link macro and add "#<anchorname>
      • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
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Note for Download Link of the Scroll ignore macro:

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Block Diagram

Scroll Title
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titleFigure 1: TE0714 block diagram
Scroll Ignore
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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below
Scroll Title
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titleFigure 2: TE0714 main components
Scroll Ignore

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Initial Delivery State

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anchorTable_InitialOV_Delivery_StateIDS
titleTable 1: Initial delivery state of programmable devices on the module.

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Storage device name

Content

Notes

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed


SPI Flash main array

demo design


eFUSE USER

Not programmed


eFUSE Security

Not programmed



Control Signals

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  • Overview of Boot Mode, Reset, Enables,
Boot process is controlled by signals on the board to board (B2B) connector.
Scroll Title
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titleTable 2: Boot signals.

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SignalDirection

Signal State

Description

BOOTMODE


input

high or open

Master SPI, x4 Mode

low or ground

Slave SelectMAP

PROG_Binputpulsed lowClear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge).
DONEoutputhighCompletion of configuration sequence.






Note

SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.


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JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1. 


Scroll Title
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titleTable 3: JTAG signals.

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Signal Name

B2B Pin

TCKJM1:89
TDIJM1:85
TDOJM1:87
TMS

JM1:91

On-board LED

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:There is one LED on TE0714 module.

Scroll Title
anchorTable_SIP_LEDsB2B
titleTable 4: LED connection.B2B I/Os

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LED

Color

FPGA

Notes

D4

Red

K18

User programmable

Clock

...

anchorTable_Clocks
titleTable 5: Clock signals.

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Clock

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Default Frequency

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IC

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FPGA

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Notes

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25 MHz

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U8

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T14

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125MHz

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U2

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B6/B5

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Frequency depends on the module variant

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
14JM16VCCIO_0
14JM236VCCIO_0NB! 17 LVDS pairs possible.
15JM248VCCIO15Supplied by the baseboard.
34JM148VCCIO34Supplied by the baseboard.
216JM116

MGT_AVCC

MGT_AVTT

4 x GTP lanes.

Please refer to the Pin-out  tables page for additional information. 

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

Quad SPI Flash

On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

Note

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant.

On-board LED

There is one LED on TE0714 module.

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title
anchorTable_B2BOBP_LEDs
titleTable 6: B2B I/OsLED connection.

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
14JM16VCCIO_0
14JM236VCCIO_0NB! 17 LVDS pairs possible.
15JM248VCCIO15Supplied by the baseboard.
34JM148VCCIO34Supplied by the baseboard.
216JM116

MGT_AVCC

MGT_AVTT

4 x GTP lanes.

Please refer to the Pin-out  tables page for additional information. 

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

Quad SPI Flash

On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

true

LED

Color

FPGA

Notes

D4

Red

K18

User programmable

Clock

Scroll Title
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titleClock signals.

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Clock

Default Frequency

IC

FPGA

Notes

CLK25MHz

25 MHz

U8

T14

Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank.
MGT_CLK

125MHz

U2

B6/B5

Frequency depends on the module variant

Note
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant.


Power and Power-On Sequence

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Power Consumption

Scroll Title
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titleTable 7: Power Consumption

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Test Condition (25 °C ambient)VIN Current mANotes
TE0714-35, TEBT0714, empty design, GT not enabled110mA

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Power Distribution Dependencies

Scroll Title
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titleFigure 3: Power Distribution
Scroll Ignore

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Scroll Only

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Scroll Title
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titleFigure 4: Power-On Sequency
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Power Rails

Scroll Title
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titleTable 8: Power Rails

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Voltages on B2B-

Connector

B2B JM1-Pin

B2B JM1-Pin

DirectionNote
VIN98, 100-inputsupply voltage
VCCIO_0-54inputhigh range bank voltage
VCCIO_15-53inputhigh range bank voltage
VCCIO_3462-inputhigh range bank voltage
3.3V84-outputinternal 3.3V voltage level
1.8V-17outputinternal 1.8V voltage level

Bank Voltages

Scroll Title
anchorTable_BankPWR_VoltagesBV
titleTable 9: Bank Voltages

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Bank

Voltage

Notes

0 Config and B14

1.8V or 3.3V

Depends on module variant

15

User

Supplied from baseboard via B2B connector, max 3.3V

34

User

Supplied from baseboard via B2B connector, max 3.3V

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Absolute Maximum Ratings

Scroll Title
anchorTable_AbsoluteTS_Maximum_RatingsAMR
titleTable 10: Module absolute maximum ratings.

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ParameterMinMaxUnitsReference Document

VIN supply voltage

-0.1

6.0

V

-
HR I/O banks supply voltage (VCCO)-0.53.6VXilinx datasheet DS181
HR I/O banks input voltage-0.4VCCO + 0.55VXilinx datasheet DS181
GTP transceivers Tx/Rx input voltage-0.51.26VXilinx datasheet DS181

Voltage on module JTAG pins

-0.4

VCCO_0 + 0.55

V

Xilinx datasheet DS181

Storage temperature

-40

+85

°C

-

Recommended Operating Conditions

Scroll Title
anchorTable_Recommended_OperatingTS_ConditionsROC
titleTable 11: Recommended Operating Conditions

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.1353.45V-
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.20VXilinx datasheet DS181
Voltage on module JTAG pins3.1353.465VXilinx datasheet DS181

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Scroll Title
anchorFigure_PhysicalTS_DimensionsPD
titleFigure 5: Physical dimensions drawing

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Scroll Title
anchorTable_TEVCP_Shop_OverviewSO
titleTable 12: Trenz Electronic Shop Overview

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Trenz shop TE0714 overview page
English pageGerman page

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Hardware Revision History

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anchorTable_HardwareRH_Revision_HistoryHRH
titleTable 13: Hardware Revision History

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DateRevisionPCNDocumentation LinkNote
2016-08-0402PCN-20160815TE0714-02VCCIO0 added to B2B

01

-TE0714-01

-

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Document Change History

Scroll Title
anchorTable_DocumentRH_Change_HistoryDCH
titleTable 14: Document change history

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Date

Revision

Authors

Description

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  • Updated to TRM version 2.2
  • Style modifications

v.48Martin Rohrmüller
  • Updated to TRM version 2.1
  • Updated B2B Connectors
  • Style modifications
2018-09-17V

v.38

Martin Rohrmüller
  • Added power rail section
  • Added Rev 02 Flash PCN
  • Corrected table headings
2018-09-17v.36Martin Rohrmüller
  • Update to TRM version 2.0 with DrawIO Figures

  • Added Figure Power Distribution
2018-04-04

v.35

Martin RohrmüllerCorrected clock net designator in table.
2017-05-28
V

v.27

Jan Kumann
  • Board-to-Board I/O section added.
  • New physical dimensions images.
  • Documents sections rearranged.
2017-03-20

Vv.26

John Hartfiel
  • Notes on Clocking section.
2017-01-27v.25Jan Kumann
  • New block diagram.
2016-12-01

v.17

Jan Kumann
  • Changes in the document structure, few corrections.
2016-11-18
v.14

Thorsten Trenz, Emmanuel Vassilakis

  • Hardware revision 02 specific changes.

2016-06-01

v.9

Antti Lukats

  • Initial version.

Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices

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