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Template Revision 2.2

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"

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<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

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        Create DrawIO object here: Attention if you copy from other page, use

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        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

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        ExampleComment
        12
      • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

        • <type>_<main section>_<name>

          • type: Figure, Table
          • main section:
            • "OV" for Overview
            • "SIP" for Signal Interfaces and Pins,
            • "OBP" for On board Peripherals,
            • "PWR" for Power and Power-On Sequence,
            • "B2B" for Board to Board Connector,
            • "TS" for Technical Specification
            • "VCP" for Variants Currently in Production
            •  "RH" for Revision History
          • name: custom, some fix names, see below
        • Fix names:
          • "Figure_OV_BD" for Block Diagram

          • "Figure_OV_MC" for Main Components

          • "Table_OV_IDS" for Initial Delivery State

          • "Table_PWR_PC" for Power Consumption

          • "Figure_PWR_PD" for Power Distribution
          • "Figure_PWR_PS" for Power Sequence
          • "Figure_PWR_PM" for Power Monitoring
          • "Table_PWR_PR" for Power Rails
          • "Table_PWR_BV" for Bank Voltages
          • "Table_TS_AMR" for Absolute_Maximum_Ratings

          • "Table_TS_ROC" for Recommended_Operating_Conditions

          • "Figure_TS_PD" for Physical_Dimensions
          • "Table_VCP_SO" for TE_Shop_Overview
          • "Table_RH_HRH" for Hardware_Revision_History

          • "Table_RH_DCH" for Document_Change_History
      • Use Anchor in the document: add link macro and add "#<anchorname>
      • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
  • ...
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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

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Download PDF version of this document.

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Table of Contents

Table of Contents

Overview

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Notes :


The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. TE0714 is the smallest module with transceiver (3 x 4 cm).

Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • List of key features of the PCB
  • Xilinx Artix-7 FPGA (A15T, A35T, A50T)

  • Rugged for shock and high vibration
  • 16 MByte QSPI Flash memory
  • Differential MEMS oscillator for MGT clocking
  • MEMS oscillator for PL clocks (Optional)
  • Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
    • 144 FPGA I/O's (Max 68 differential)
    • XADC analog input
    • 4 GTP (high-performance transceiver) lanes
    • GT reference clock inputs
    • Optimized I/O and power pins for good signal integrity
  • On-board high-efficiency DC-DC converters
  • Power supply for all on-board components
  • eFUSE bit-stream encryption (AES)
  • One user configurable LED

Different configurations for cost and performance optimization available upon request. Available options are:

  • FPGA Type (A15T, A35T, A50T), temperature grade
  • GT clock frequency (or none if not implemented)
  • PL clock frequency and precision (or none if not implemented)
  • Config and B14 bank Voltage: 1.8V or 3.3V
  • SPI Flash type (or none if not implemented)
  • LED Color (or none if not implemented)
  • PUDC Pin strapping (pull high or pull down)
  • GT power enable pin strapping (default power enabled or disabled)

Block Diagram

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borderfalse
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fitWindowfalse
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diagramNameBD-TE0714-02
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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below
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titleTE0714 main components
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draw.io Diagram
borderfalse
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fitWindowfalse
diagramDisplayName
lboxtrue
revision2
diagramNameMC-TE0714
simpleViewertrue
width
linksauto
tbstyletop
diagramWidth641

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  1. Xilinx Artix-7 FPGA (XC7A series), U4
  2. 16 MByte SPI Flash, U7
  3. B2B connector Samtec Razor Beam™ LSHM-150, JM2
  4. B2B connector Samtec Razor Beam™ LSHM-150, JM1
  5. 25 MHz oscillator, U8
  6. Single output low-dropout linear regulator (1.2V_MGT), U6
  7. Single output low-dropout linear regulator (1.0V_MGT), U5
  8. Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
  9. Red indication LED, D4
  10. Step-down DC-DC converter (1.0V), U1
  11. PFET load switch with configurable slew rate (3.3V), Q1
  12. Low-power step-down DC-DC converter (1.8V), U3
  13. Voltage detector for circuit initialization and timing supervision, U23 


Initial Delivery State

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titleInitial delivery state of programmable devices on the module.

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Storage device name

Content

Notes

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed


SPI Flash main array

demo design


eFUSE USER

Not programmed


eFUSE Security

Not programmed



Control Signals

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  • Overview of Boot Mode, Reset, Enables,
Boot process is controlled by signals on the board to board (B2B) connector.
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titleBoot signals.

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SignalDirection

Signal State

Description

BOOTMODE


input

high or open

Master SPI, x4 Mode

low or ground

Slave SelectMAP

PROG_Binputpulsed lowClear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge).
DONEoutputhighCompletion of configuration sequence.
Note

SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.


Signals, Interfaces and Pins

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Notes :

  • For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

JTAG Interface

JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1. 


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Signal Name

B2B Pin

TCKJM1:89
TDIJM1:85
TDOJM1:87
TMS

JM1:91

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
14JM16VCCIO_0
14JM236VCCIO_0NB! 17 LVDS pairs possible.
15JM248VCCIO15Supplied by the baseboard.
34JM148VCCIO34Supplied by the baseboard.
216JM116

MGT_AVCC

MGT_AVTT

4 x GTP lanes.

Please refer to the Pin-out  tables page for additional information. 

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

Quad SPI Flash

On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

Note

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant.

On-board LED

There is one LED on TE0714 module.

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titleLED connection.

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LED

Color

FPGA

Notes

D4

Red

K18

User programmable

Clock

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Clock

Default Frequency

IC

FPGA

Notes

CLK25MHz

25 MHz

U8

T14

Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank.
MGT_CLK

125MHz

U2

B6/B5

Frequency depends on the module variant


Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

TE0714 needs one single power supply with nominal of 3.3V.

Power Consumption

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titlePower Consumption

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Test Condition (25 °C ambient)VIN Current mANotes
TE0714-35, TEBT0714, empty design, GT not enabled110mA

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

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draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision6
diagramNamePD-TE0714
simpleViewertrue
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linksauto
tbstyletop
diagramWidth641

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Power-On Sequence

There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.

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borderfalse
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diagramNameTE0714-02_Power_Sequenz
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width
linksauto
tbstyletop
diagramWidth641

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Power Rails

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Voltages on B2B-

Connector

B2B JM1-Pin

B2B JM1-Pin

DirectionNote
VIN98, 100-inputsupply voltage
VCCIO_0-54inputhigh range bank voltage
VCCIO_15-53inputhigh range bank voltage
VCCIO_3462-inputhigh range bank voltage
3.3V84-outputinternal 3.3V voltage level
1.8V-17outputinternal 1.8V voltage level

Bank Voltages

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Bank

Voltage

Notes

0 Config and B14

1.8V or 3.3V

Depends on module variant

15

User

Supplied from baseboard via B2B connector, max 3.3V

34

User

Supplied from baseboard via B2B connector, max 3.3V

Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

Include Page
3 x 4 SoM LSHM B2B Connectors
3 x 4 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

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titleModule absolute maximum ratings.

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ParameterMinMaxUnitsReference Document

VIN supply voltage

-0.1

6.0

V

-
HR I/O banks supply voltage (VCCO)-0.53.6VXilinx datasheet DS181
HR I/O banks input voltage-0.4VCCO + 0.55VXilinx datasheet DS181
GTP transceivers Tx/Rx input voltage-0.51.26VXilinx datasheet DS181

Voltage on module JTAG pins

-0.4

VCCO_0 + 0.55

V

Xilinx datasheet DS181

Storage temperature

-40

+85

°C

-

Recommended Operating Conditions

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.1353.45V-
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.20VXilinx datasheet DS181
Voltage on module JTAG pins3.1353.465VXilinx datasheet DS181

Physical Dimensions

  • Module size: 40 mm × 30 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm

  • PCB thickness: 1.6 mm

  • Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.

All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.

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titlePhysical dimensions drawing

Variants Currently In Production

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titleTrenz Electronic Shop Overview

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Trenz shop TE0714 overview page
English pageGerman page
Note

On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module.

Revision History

Hardware Revision History

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DateRevisionPCNDocumentation LinkNote
2016-08-0402PCN-20160815TE0714-02VCCIO0 added to B2B

01

-TE0714-01

-

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

 

Document Change History

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titleDocument change history

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Date

Revision

Authors

Description

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  • Updated to TRM version 2.2
  • Style modifications

v.48Martin Rohrmüller
  • Updated to TRM version 2.1
  • Updated B2B Connectors
  • Style modifications
2018-09-17

v.38

Martin Rohrmüller
  • Added power rail section
  • Added Rev 02 Flash PCN
  • Corrected table headings
2018-09-17v.36Martin Rohrmüller
  • Update to TRM version 2.0 with DrawIO Figures

  • Added Figure Power Distribution
2018-04-04

v.35

Martin RohrmüllerCorrected clock net designator in table.
2017-05-28

v.27

Jan Kumann
  • Board-to-Board I/O section added.
  • New physical dimensions images.
  • Documents sections rearranged.
2017-03-20

v.26

John Hartfiel
  • Notes on Clocking section.
2017-01-27v.25Jan Kumann
  • New block diagram.
2016-12-01

v.17

Jan Kumann
  • Changes in the document structure, few corrections.
2016-11-18
v.14

Thorsten Trenz, Emmanuel Vassilakis

  • Hardware revision 02 specific changes.

2016-06-01

v.9

Antti Lukats

  • Initial version.

Disclaimer

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