TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"
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Important General Note:
If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template:
Scroll Title
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Figure_anchorname
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Create DrawIO object here: Attention if you copy from other page, use
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed
Table template:
Layout macro can be use for landscape of large tables
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Example
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The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
type: Figure, Table
main section:
"OV" for Overview
"SIP" for Signal Interfaces and Pins,
"OBP" for On board Peripherals,
"PWR" for Power and Power-On Sequence,
"B2B" for Board to Board Connector,
"TS" for Technical Specification
"VCP" for Variants Currently in Production
"RH" for Revision History
name: custom, some fix names, see below
Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
"Figure_PWR_PD" for Power Distribution
"Figure_PWR_PS" for Power Sequence
"Figure_PWR_PM" for Power Monitoring
"Table_PWR_PR" for Power Rails
"Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
"Figure_TS_PD" for Physical_Dimensions
"Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
"Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. TE0714 is the smallest module with transceiver (3 x 4 cm).
Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.
Key Features
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Notes :
List of key features of the PCB
Xilinx Artix-7 FPGA (A15T, A35T, A50T)
Rugged for shock and high vibration
16 MByte QSPI Flash memory
Differential MEMS oscillator for MGT clocking
MEMS oscillator for PL clocks (Optional)
Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
144 FPGA I/O's (Max 68 differential)
XADC analog input
4 GTP (high-performance transceiver) lanes
GT reference clock inputs
Optimized I/O and power pins for good signal integrity
On-board high-efficiency DC-DC converters
Power supply for all on-board components
eFUSE bit-stream encryption (AES)
One user configurable LED
Different configurations for cost and performance optimization available upon request. Available options are:
FPGA Type (A15T, A35T, A50T), temperature grade
GT clock frequency (or none if not implemented)
PL clock frequency and precision (or none if not implemented)
Config and B14 bank Voltage: 1.8V or 3.3V
SPI Flash type (or none if not implemented)
LED Color (or none if not implemented)
PUDC Pin strapping (pull high or pull down)
GT power enable pin strapping (default power enabled or disabled)
Block Diagram
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Figure_OV_BD
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TE0714 block diagram
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BD-TE0714-02
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Main Components
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Notes :
Picture of the PCB (top and bottom side) with labels of important components
Add List below
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Figure_OV_MC
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TE0714 main components
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Xilinx Artix-7 FPGA (XC7A series), U4
16 MByte SPI Flash, U7
B2B connector Samtec Razor Beam™ LSHM-150, JM2
B2B connector Samtec Razor Beam™ LSHM-150, JM1
25 MHz oscillator, U8
Single output low-dropout linear regulator (1.2V_MGT), U6
Single output low-dropout linear regulator (1.0V_MGT), U5
Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
Red indication LED, D4
Step-down DC-DC converter (1.0V), U1
PFET load switch with configurable slew rate (3.3V), Q1
Low-power step-down DC-DC converter (1.8V), U3
Voltage detector for circuit initialization and timing supervision, U23
Initial Delivery State
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Table_OV_IDS
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Initial delivery state of programmable devices on the module.
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Storage device name
Content
Notes
SPI Flash OTP Area
Empty, not programmed
Except serial number programmed by flash vendor
SPI Flash Quad Enable bit
Programmed
SPI Flash main array
demo design
eFUSE USER
Not programmed
eFUSE Security
Not programmed
Control Signals
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Overview of Boot Mode, Reset, Enables,
Boot process is controlled by signals on the board to board (B2B) connector.
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Table_OV_BS
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Boot signals.
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Signal
Direction
Signal State
Description
BOOTMODE
input
high or open
Master SPI, x4 Mode
low or ground
Slave SelectMAP
PROG_B
input
pulsed low
Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge).
DONE
output
high
Completion of configuration sequence.
Note
SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.
Signals, Interfaces and Pins
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Notes :
For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
JTAG
UART
I2C
MGT
...
JTAG Interface
JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.
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Table_SIP_JTAG
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JTAG signals.
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Signal Name
B2B Pin
TCK
JM1:89
TDI
JM1:85
TDO
JM1:87
TMS
JM1:91
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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B2B I/Os
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FPGA Bank
B2B Connector
I/O Signal Count
Voltage Level
Notes
14
JM1
6
VCCIO_0
14
JM2
36
VCCIO_0
NB! 17 LVDS pairs possible.
15
JM2
48
VCCIO15
Supplied by the baseboard.
34
JM1
48
VCCIO34
Supplied by the baseboard.
216
JM1
16
MGT_AVCC
MGT_AVTT
4 x GTP lanes.
Please refer to the Pin-out tables page for additional information.
On-board Peripherals
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Notes :
add subsection for every component which is important for design, for example:
Ethernet PHY
USB PHY
Programmable Clock Generator
Oscillators
eMMCs
RTC
FTDI
...
DIP-Switches
Buttons
LEDs
Quad SPI Flash
On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
Note
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant.
On-board LED
There is one LED on TE0714 module.
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Table_OBP_LEDs
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LED connection.
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LED
Color
FPGA
Notes
D4
Red
K18
User programmable
Clock
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Table_OBP_Clocks
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Clock signals.
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Clock
Default Frequency
IC
FPGA
Notes
CLK25MHz
25 MHz
U8
T14
Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank.
MGT_CLK
125MHz
U2
B6/B5
Frequency depends on the module variant
Power and Power-On Sequence
To power-up a module, power supply with minimum current capability of 1A is recommended.
TE0714 needs one single power supply with nominal of 3.3V.
Power Consumption
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Table_PWR_PC
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Power Consumption
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Test Condition (25 °C ambient)
VIN Current mA
Notes
TE0714-35, TEBT0714, empty design, GT not enabled
110mA
Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
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Figure_PWR_PD
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Power Distribution
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Power-On Sequence
There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.
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Power-On Sequency
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Power Rails
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Table_PWR_PR
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Power Rails
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Voltages on B2B-
Connector
B2B JM1-Pin
B2B JM1-Pin
Direction
Note
VIN
98, 100
-
input
supply voltage
VCCIO_0
-
54
input
high range bank voltage
VCCIO_15
-
53
input
high range bank voltage
VCCIO_34
62
-
input
high range bank voltage
3.3V
84
-
output
internal 3.3V voltage level
1.8V
-
17
output
internal 1.8V voltage level
Bank Voltages
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Table_PWR_BV
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Bank Voltages
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Bank
Voltage
Notes
0 Config and B14
1.8V or 3.3V
Depends on module variant
15
User
Supplied from baseboard via B2B connector, max 3.3V
34
User
Supplied from baseboard via B2B connector, max 3.3V
Board to Board Connectors
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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors
On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module.