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Table of Contents
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Overview
The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. TE0714 is the smallest module with transceiver (3 x 4 cm).
Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.
Key Features
Xilinx Artix-7 FPGA (A15T, A35T, A50T)
- Rugged for shock and high vibration
- 16 MByte QSPI Flash memory
- Differential MEMS oscillator for MGT clocking
- MEMS oscillator for PL clocks (Optional)
- Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
- 138 FPGA I/O's (Max 68 differential)
5 IO's (QSPI or user I/O's)
- XADC analog input
- 4 GTP (high-performance transceiver) lanes
- GT reference clock inputs
- Optimized I/O and power pins for good signal integrity
- On-board high-efficiency DC-DC converters
- Power supply for all on-board components
- eFUSE bit-stream encryption (AES)
- One user configurable LED
Different configurations for cost and performance optimization available upon request. Available options are:
- FPGA Type (A15T, A35T, A50T), temperature grade
- GT clock frequency (or none if not implemented)
- PL clock frequency and precision (or none if not implemented)
- Config and B14 bank Voltage: 1.8V or 3.3V
- SPI Flash type (or none if not implemented)
- LED Color (or none if not implemented)
- PUDC Pin strapping (pull high or pull down)
- GT power enable pin strapping (default power enabled or disabled)
Block Diagram
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Main Components
- Xilinx Artix-7 FPGA (XC7A series), U4
- 16 MByte SPI Flash, U7
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 25 MHz oscillator, U8
- Single output low-dropout linear regulator (1.2V_MGT), U6
- Single output low-dropout linear regulator (1.0V_MGT), U5
- Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
- Red indication LED, D4
- Step-down DC-DC converter (1.0V), U1
- PFET load switch with configurable slew rate (3.3V), Q1
- Low-power step-down DC-DC converter (1.8V), U3
- Voltage detector for circuit initialization and timing supervision, U23
Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
eFUSE USER | Not programmed | |
eFUSE Security | Not programmed |
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
---|---|---|---|---|
14 | JM1 | 6 | VCCIO_0 | |
14 | JM2 | 36 | VCCIO_0 | NB! 17 LVDS pairs possible. |
14 | JM2 | 5 | VCCIO_0 | used for QSPI flash |
15 | JM2 | 48 | VCCIO15 | Supplied by the baseboard. |
34 | JM1 | 48 | VCCIO34 | Supplied by the baseboard. |
216 | JM1 | 16 | MGT_AVCC MGT_AVTT | 4 x GTP lanes. |
Please refer to the Pin-out tables page for additional information.
JTAG Interface
JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.
Signal Name | B2B Pin |
---|---|
TCK | JM1:89 |
TDI | JM1:85 |
TDO | JM1:87 |
TMS | JM1:91 |
On-board LED's
There is one LED on TE0714 module:
LED | Color | FPGA | Notes |
---|---|---|---|
D4 | Red | K18 |
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Clocking
Clock | Default Frequency | IC | FPGA | Notes |
---|---|---|---|---|
CLK25MHz | 25 MHz | U8 | T14 | Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank. |
MGT_CLK | 125MHz | U2 | B6/B5 | Frequency depends on the module variant |
Boot Process
Boot mode is controlled by the MODE signal on the board to board (B2B) connector:
MODE signal State | Boot Mode |
---|---|
high or open | Master SPI, x4 Mode |
low or ground | Slave SelectMAP |
Note |
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SPI D2 and D3 have no pull-ups on the module so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
On-board Peripherals
16 MByte Quad SPI Flash
On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
Note |
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant. |
Power and Power-On Sequence
To power-up a module, power supply with minimum current capability of 1A is recommended.
Power Supply
TE0714 needs one single power supply with nominal of 3.3V.
Power Consumption
Test Condition (25 °C ambient) | VIN Current mA | Notes |
---|---|---|
TE0714-35, TEBT0714, empty design, GT not enabled | 110mA |
Actual power consumption depends on the FPGA design and ambient temperature.
Power-On Sequence
There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.
Bank Voltages
Bank | Voltage | Notes |
---|---|---|
0 Config and B14 | 1.8V or 3.3V | Depends on module variant |
15 | User | Supplied from baseboard via B2B connector, max 3.3V |
34 | User | Supplied from baseboard via B2B connector, max 3.3V |
Board to Board Connectors
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Variants Currently In Production
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Module Variant | FPGA Chip Model | B14/Config Voltage [V] | R27 (VCCIO_0 on JM2 Pin 54) | SPI Flash |
---|---|---|---|---|
TE0714-02-35-2I | XC7A35T-2CSG325I | 3.3 | JM2 Pin 54 = VCCIO_0 (3.3 V) | S25FL127S |
TE0714-02-35-2IC6 | XC7A35T-2CSG325I | 1.8 | JM2 Pin 54 = Open | N25Q128 |
TE0714-02-50-2I | XC7A50T-2CSG325I | 3.3 | JM2 Pin 54 = VCCIO_0 (3.3 V) | S25FL127S |
TE0714-02-50-2IC6 | XC7A50T-2CSG325I | 1.8 | JM2 Pin 54 = Open | N25Q128 |
Note |
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On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module. |
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
---|---|---|---|---|
VIN supply voltage | -0.1 | 6.0 |
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- "OV" for Overview
- "SIP" for Signal Interfaces and Pins,
- "OBP" for On board Peripherals,
- "PWR" for Power and Power-On Sequence,
- "B2B" for Board to Board Connector,
- "TS" for Technical Specification
- "VCP" for Variants Currently in Production
- "RH" for Revision History
- name: custom, some fix names, see below
- Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
- "Figure_PWR_PD" for Power Distribution
- "Figure_PWR_PS" for Power Sequence
- "Figure_PWR_PM" for Power Monitoring
- "Table_PWR_PR" for Power Rails
- "Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
- "Figure_TS_PD" for Physical_Dimensions
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Table of Contents
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Overview
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Notes :
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The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. TE0714 is the smallest module with transceiver (3 x 4 cm).
Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.
Key Features
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Notes :
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Xilinx Artix-7 FPGA (A15T, A35T, A50T)
- Rugged for shock and high vibration
- 16 MByte QSPI Flash memory
- Differential MEMS oscillator for MGT clocking
- MEMS oscillator for PL clocks (Optional)
- Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
- 144 FPGA I/O's (Max 68 differential)
- XADC analog input
- 4 GTP (high-performance transceiver) lanes
- GT reference clock inputs
- Optimized I/O and power pins for good signal integrity
- On-board high-efficiency DC-DC converters
- Power supply for all on-board components
- eFUSE bit-stream encryption (AES)
- One user configurable LED
Different configurations for cost and performance optimization available upon request. Available options are:
- FPGA Type (A15T, A35T, A50T), temperature grade
- GT clock frequency (or none if not implemented)
- PL clock frequency and precision (or none if not implemented)
- Config and B14 bank Voltage: 1.8V or 3.3V
- SPI Flash type (or none if not implemented)
- LED Color (or none if not implemented)
- PUDC Pin strapping (pull high or pull down)
- GT power enable pin strapping (default power enabled or disabled)
Block Diagram
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Main Components
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- Xilinx Artix-7 FPGA (XC7A series), U4
- 16 MByte SPI Flash, U7
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 25 MHz oscillator, U8
- Single output low-dropout linear regulator (1.2V_MGT), U6
- Single output low-dropout linear regulator (1.0V_MGT), U5
- Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
- Red indication LED, D4
- Step-down DC-DC converter (1.0V), U1
- PFET load switch with configurable slew rate (3.3V), Q1
- Low-power step-down DC-DC converter (1.8V), U3
- Voltage detector for circuit initialization and timing supervision, U23
Initial Delivery State
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module. |
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Storage device name
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Content
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Notes
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SPI Flash OTP Area
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Empty, not programmed
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Except serial number programmed by flash vendor
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SPI Flash Quad Enable bit
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Programmed
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SPI Flash main array
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demo design
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eFUSE USER
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Not programmed
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eFUSE Security
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Not programmed
Control Signals
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anchor | Table_OV_BS |
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title | Boot signals. |
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Signal State
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Description
BOOTMODE
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high or open
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Master SPI, x4 Mode
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low or ground
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Slave SelectMAP
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Note |
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SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
Signals, Interfaces and Pins
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JTAG Interface
JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.
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anchor | Table_SIP_JTAG |
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title | JTAG signals. |
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Signal Name
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B2B Pin
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JM1:91
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_SIP_B2B |
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title | B2B I/Os |
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MGT_AVCC
MGT_AVTT
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Please refer to the Pin-out tables page for additional information.
On-board Peripherals
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Quad SPI Flash
On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
Note |
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant. |
On-board LED
There is one LED on TE0714 module.
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anchor | Table_OBP_LEDs |
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title | LED connection. |
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LED
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Color
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FPGA
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Notes
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D4
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Red
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K18
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User programmable
Clock
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title | Clock signals. |
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Clock
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Default Frequency
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IC
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FPGA
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Notes
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25 MHz
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U8
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T14
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125MHz
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U2
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B6/B5
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Frequency depends on the module variant
Power and Power-On Sequence
To power-up a module, power supply with minimum current capability of 1A is recommended.
TE0714 needs one single power supply with nominal of 3.3V.
Power Consumption
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title | Power Consumption |
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Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
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title | Power Distribution |
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Power-On Sequence
There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.
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anchor | Figure_PWR_PS |
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title | Power-On Sequency |
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Power Rails
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anchor | Table_PWR_PR |
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title | Power Rails |
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Voltages on B2B-
Connector
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B2B JM1-Pin
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B2B JM1-Pin
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Bank Voltages
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anchor | Table_PWR_BV |
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title | Bank Voltages |
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Bank
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Voltage
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Notes
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0 Config and B14
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1.8V or 3.3V
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15
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User
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Supplied from baseboard via B2B connector, max 3.3V
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34
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User
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Board to Board Connectors
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Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title | Module absolute maximum ratings. |
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VIN supply voltage
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-0.1
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6.0
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V
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Voltage on module JTAG pins
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-0.4
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V
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Storage temperature
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-40
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+85
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°C
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Recommended Operating Conditions
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anchor | Table_TS_ROC |
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title | Recommended Operating Conditions |
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V | - | |
HR I/O banks supply voltage (VCCO) |
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-0. |
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5 | 3. |
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6 | V | Xilinx datasheet DS181 |
HR I/O banks input voltage | -0. |
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4 | VCCO + 0.55 |
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V | Xilinx datasheet DS181 |
Physical Dimensions
Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.
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Variants Currently In Production
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title | Trenz Electronic Shop Overview |
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Note |
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On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module. |
Revision History
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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GTP transceivers Tx/Rx input voltage | -0.5 | 1.26 | V | Xilinx datasheet DS181 |
Voltage on module JTAG pins | -0.4 | VCCO_0 + 0.55 | V | Xilinx datasheet DS181 |
Storage temperature | -40 | +85 | °C | - |
Recommended Operating Conditions
Parameter | Min | Max | Units | Notes |
---|---|---|---|---|
VIN supply voltage | 3.135 | 3.45 | V | - |
HR I/O banks supply voltage (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS181 |
HR I/O banks input voltage | -0.20 | VCCO + 0.20 | V | Xilinx datasheet DS181 |
Voltage on module JTAG pins | 3.135 | 3.465 | V | Xilinx datasheet DS181 |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Note |
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Please check Xilinx datasheet DS181 for complete list of absolute maximum and recommended operating ratings for the Artix-7. |
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Physical Dimensions
Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.
Revision History
Hardware Revision History
Date | Revision | Notes | PCN Link | Documentation Link |
---|---|---|---|---|
2016-08-04 | 02 | VCCIO0 added to B2B | PCN-20160815 | TE0714-02 |
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01 | - |
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Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
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Document Change History
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Disclaimer
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