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Template Revision 2.4 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"


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Basic Notes
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
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Table of contents

Table of Contents
outlinetrue

Overview

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General Design description
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ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.

Key Features

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Excerpt
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • FMeter
  • User LED (PCB REV03 only)
  • Modified FSBL for SI5338 programming
  • Special FSBL for QSPI programming

Revision History

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...

TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip

TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip

...

  • new assembly variants
  • update optional petalinux startup init script

...

  • correction:
    • TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised
    • small changes on DDR setup of TE0820-02-2EG-1EE

...

  • different design for REV03
  • small petalinux changes
  • IO renaming
  • additional notes for FSBL generated with Win SDK
  • changed *.bif

...

  • bugfix board part files BANK1 MIO voltages
  • Add "dummy" PS USB3 parameter so solve problems with some USB2 devices

...

TE0820-test_board-vivado_2017.4-build_10_20180524151356.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180524151342.zip

...

  • solved Linux Flash issue
  • new assembly variant

...

  • new assembly variants

...

  • solved JTAG/Linux issue

...

  • board part csv update

...

  • rework board part files
  • solved  USB, QSPI and PHy issue
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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
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        ExampleComment
        12



  • ...


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Table of contents

Table of Contents
outlinetrue

Overview

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Notes :


ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0820-info

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • FMeter
  • MAC from EEPROM
  • User LED (PCB REV03 only)
  • Modified FSBL for SI5338 programming
  • Special FSBL for QSPI programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description



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DateVivadoProject BuiltAuthorsDescription
2019-02-212018.3


John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • SI5338 CLKBuilder Pro Project
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
2018-10-312018.2

TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip

TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip

John Hartfiel
  • new assembly variants
  • update optional petalinux startup init script
2018-09-122018.2TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20180912094615.zip
TE0820-test_board-vivado_2018.2-build_03_20180912094558.zip
John Hartfiel
  • correction:
    • TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised
    • small changes on DDR setup of TE0820-02-2EG-1EE
2018-08-152018

...

.2TE0820-test_board-vivado_

...

2018.2-build_

...

01_

...

20180706212937.zip
TE0820-test_board_noprebuilt-vivado_

...

2018.2-build_

...

01_

...

20180706212952.zipJohn Hartfiel

...

  • solved SD SDX Cards Problem
  • Separate csv name for all assembly variants
  • different design for REV03
  • small petalinux changes
  • IO renaming
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-06-192017.4

...

TE0820-test_board-vivado_2017.

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4-build_

...

10_

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20180619160713.zip
TE0820-test_board_noprebuilt-vivado_2017.

...

4-build_

...

10_

...

20180619160728.zipJohn Hartfiel

...

  • solved SD WP Problem
  • bugfix board part files BANK1 MIO voltages
  • Add "dummy" PS USB3 parameter so solve problems with some USB2 devices
2018-05-242017.4

...

TE0820-test_board-vivado_2017.

...

4-build_

...

10_

...

20180524151356.zip
TE0820-test_board_noprebuilt-vivado_2017.

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4-build_

...

10_

...

20180524151342.zip

John Hartfiel

...

  • initial release

Release Notes and Know Issues

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Do not use HW Manager connection, or if debugging is nessecary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal

...

Requirements

Software

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Hardware

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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

  •  use slower DDR speed
  • Xilinx has stopped ES1 support with 2018.2, please use 2017.4 reference design for ES1

...

TE0820-02-2CG-1E

...

Design supports following carriers:

...

...

...

...

...

  • Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
  • No SD Slot available, pins goes to Pin Header
  • For TEBA0841 REV01, please contact TE support
  • solved Linux Flash issue
  • new assembly variant
2018-04-252017.4TE0820-test_board-vivado_2017.4-build_07_20180425134435.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_07_20180425134459.zip
John Hartfiel
  • new assembly variants
2018-02-062017.4TE0820-test_board-vivado_2017.4-build_06_20180206203359.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_06_20180206203414.zip
John Hartfiel
  • solved JTAG/Linux issue
2018-02-012017.4TE0820-test_board-vivado_2017.4-build_05_20180201084319.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180201094724.zip
John Hartfiel
  • board part csv update
2018-01-242017.4TE0820-test_board-vivado_2017.4-build_05_20180124085247.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180124085303.zip
John Hartfiel
  • rework board part files
  • solved  USB, QSPI and PHy issue
2017-11-212017.2TE0820-test_board-vivado_2017.2-build_05_20171121160552.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171121160606.zip
John Hartfiel
  • solved SD SDX Cards Problem
  • Separate csv name for all assembly variants
2017-11-202017.2TE0820-test_board-vivado_2017.2-build_05_20171120162931.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171120162851.zip
John Hartfiel
  • solved SD WP Problem
2017-10-192017.2TE0820-test_board-vivado_2017.2-build_05_20171019104824.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171019104837.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

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  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed


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IssuesDescriptionWorkaroundTo be fixed version
Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 update
USB UART Terminal is blocked / SDK Debugging is blockedThis happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is nessecary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal
Solved with 20180206 update


Requirements

Software

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Notes :

  • list of software which was used to generate the design


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SoftwareVersionNote
Vivado2018.3needed
SDK2018.3needed
PetaLinux2018.3needed
SI ClockBuilder Pro---optional


Hardware

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  • list of software which was used to generate the design



Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0820-ES1           es1            REV01     1GB      64MB      4GB        NA                     Not longer supported by vivado   
TE0820-02-02EG-1E    2eg_1e_1gb     REV02     1GB      64MB      4GB        NA                     NA                                 
TE0820-02-02EG-1E3   2eg_1e_1gb     REV02     1GB      64MB      4GB        2.5 mm connectors    NA                                 
TE0820-02-02CG-1E    2cg_1e_1gb     REV02     1GB      64MB      4GB        NA                     NA                                 
TE0820-02-03EG-1E    3eg_1e_1gb     REV02     1GB      64MB      4GB        NA                     NA                                 
TE0820-02-03EG-1E3   3eg_1e_1gb     REV02     1GB      64MB      4GB        2.5 mm connectors    NA                                 
TE0820-02-03CG-1E    3cg_1e_1gb     REV02     1GB      64MB      4GB        NA                     NA                                 
TE0820-02-02EG-1EA   2eg_1e_1gb     REV02     1GB      128MB     4GB        NA                     NA                                 
TE0820-02-02EG-1EL   2eg_1e_1gb     REV02     1GB      128MB     4GB        2.5 mm connectors    NA                                 
TE0820-02-02CG-1EA   2cg_1e_1gb     REV02     1GB      128MB     4GB        NA                     NA                                 
TE0820-02-03EG-1EA   3eg_1e_1gb     REV02     1GB      128MB     4GB        NA                     NA                                 
TE0820-02-03EG-1EL   3eg_1e_1gb     REV02     1GB      128MB     4GB        2.5 mm connectors    NA                                 
TE0820-02-03CG-1EA   3cg_1e_1gb     REV02     1GB      128MB     4GB        NA                     NA                                 
TE0820-02-04CG-1EA   4cg_1e_1gb     REV02     1GB      128MB     4GB        NA                     NA                                 
TE0820-03-04EV-1EA   4ev_1e_2gb     REV03     2GB      128MB     4GB        NA                     NA                                 
TE0820-03-02CG-1EA   2cg_1e_2gb     REV03     2GB      128MB     4GB        NA                     NA                                 
TE0820-03-02EG-1EA   2eg_1e_2gb     REV03     2GB      128MB     4GB        NA                     NA                                 
TE0820-03-02EG-1EL   2eg_1e_2gb     REV03     2GB      128MB     4GB        2.5 mm connectors    NA                                 
TE0820-03-02CG-1ED   2cg_1e_2gb     REV03     2GB      128MB     8GB        NA                     NA                                 
TE0820-03-03CG-1ED   3cg_1e_2gb     REV03     2GB      128MB     8GB        NA                     NA                                 
TE0820-03-04CG-1ED   4cg_1e_2gb     REV03     2GB      128MB     8GB        NA                     NA                                 
TE0820-03-02EG-1ED   2eg_1e_2gb     REV03     2GB      128MB     8GB        NA                     NA                                 
TE0820-03-03EG-1ED   3eg_1e_2gb     REV03     2GB      128MB     8GB        NA                     NA                                 
TE0820-03-03EG-1EL   3eg_1e_2gb     REV03     2GB      128MB     4GB        NA                     NA                                 



Design supports following carriers:

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Carrier ModelNotes
TE0701
TE0703
TE0705
TE0706
TEBA0841
  • Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
  • No SD Slot available, pins goes to Pin Header
  • For TEBA0841 REV01, please contact TE support


Additional HW Requirements:

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Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct typ
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
CoolerIt's recommended to use cooler on ZynqMP device


Content

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  • content of the zip file

For general structure and of the reference design, see Project Delivery

Design Sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

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TypeLocationNotes
SI5338<design name>/misc/Si5338SI5338 Project with current PLL Configuration
init.sh<design name>/sd/Additional Initialization Script for Linux



Prebuilt

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  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Added
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
              optional "TE::pr_program_flash_binfile -swapp hello_te0820" possible
  4. Copy image.ub on SD-Card
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Insert SD-Card

SD

Use this description for CPLD Firmware with SD Boot selectable.

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD/QSPI Flash into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device
  4. Option Features
    1. Webserver to get access to Zynq
      1. insert IP on web browser to start web interface
    2. init.sh scripts
      1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)

Vivado HW Manager

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

Additional HW Requirements:

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For general structure and of the reference design, see Project Delivery

Design Sources

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Additional Sources

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Prebuilt

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<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Removed
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

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Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
              optional "TE::pr_program_flash_binfile -swapp hello_te0820" possible
  4. Copy image.ub on SD-Card
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Insert SD-Card

SD

Use this description for CPLD Firmware with SD Boot selectable.

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD/QSPI Flash into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device

...


SI5338_CLK0 Counter: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz

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titleVivado Hardware Manager
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PCB REV01, REV02 Design:

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titleVivado Hardware Manager PCB REV01,REV02
Image Modified

System Design - Vivado

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  • Description of Block Design,

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Block Design

PCB REV03

PCB REV01 REV02

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Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

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zynqmp_fsbl

TE modified 2018.2 3 FSBL

ChangesGeneral:

  • Si5338 Configuration, ETH+OTG Reset over GPIOsee xfsbl_boardModified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h, xfsbl_main/.c(search for 'TE Mod' on source code)
  • Add register_mapFiles:  te_xfsbl_hooks.h, si5338.c, si5338.h

...

  • /.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2018.2 3 FSBL

Changes:

General:

  • Modified Files: xfsbl
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation
  • see  xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c

...

  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

...

Software Design -  PetaLinux

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For PetaLinux installation and  project creation, follow instructions from:

Config

Activate:

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y

U-Boot-Boot

Start with petalinux-config -c u-boot
Changes:

  • CONFIG_ENV_IS_NOWHERE=y

  • CONFIG_ENV_IS_IN_SPI_FLASH is not set

Change platform-top.h:

Code Block
languagejs
#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000

#define DFU_ALT_INFO_RAM \
                "dfu_ram_info=" \
        "setenv dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0"h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000

#define DFU_ALT_INFO_RAM \
        "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"

#define DFU_ALT_INFO_MMC =" \
        "setenv dfu_mmcalt_info= " \
        "set dfu_alt_info image.ub ram $netstart 0x1e00000\0" \
        "${kernel_image} fatdfu_ram=run dfu_ram_info && dfu 0 1\\\\;ram 0\0" \
        "dfuthor_mmcram=run dfu_mmcram_info && dfuthordown 0 mmcram 0\0"

#define DFU_ALT_INFO_MMC \
        "thordfu_mmc=run_info=" \
        "set dfu_mmcalt_info &&" thordown\
 0 mmc 0\0"

/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif

/*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#ifdef CONFIG_ZYNQMP_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS          5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x54
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET  0x20
#endif

Device Tree

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/include/ "system-conf.dtsi"
/ {
};


/* SDIO */

&sdhci1 {
   disable-wp;
   no-1-8-v;
};

/* ETH PHY */
&gem3 {

    status = "okay";
  ethernet_phy0: ethernet-phy@0 {
 "${kernel_image} fat 0 1\\\\;" \
        "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
        "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"

/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif

/*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#define CONFIG_ZYNQMP_EEPROM
#ifdef CONFIG_ZYNQMP_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS        compatible = "marvell,88e1510";
  0
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x50
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET  0xFA
#endif



Device Tree

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/include/ "system-conf.dtsi"
/ {
};


/* SDIO */

&sdhci1 {
   disable-wp;
   no-1-8-v device_type = "ethernet-phy";
            reg = <1>;
    };
};

/* USBETH 2.0PHY */

&dwc3_0gem3 {

    status = "okay";
  ethernet_phy0:  dr_modeethernet-phy@0 {
        compatible = "hostmarvell,88e1510";
    maximum-speed    device_type = "highethernet-speedphy";
         /delete-property/phy-names;
   reg  /delete-property/phys= <1>;
    /delete-property/snps,usb3_lpm_capable};
};

/* QSPIUSB PHY2.0 */

&qspidwc3_0 {
    #address-cellsstatus = <1>"okay";
    #size-cellsdr_mode = <0>"host";
    statusmaximum-speed = "okayhigh-speed";
    flash0: flash@0 {
        compatible = "jedec,spi-nor"/delete-property/phy-names;
    /delete-property/phys;
    reg = <0x0>;
    /delete-property/snps,usb3_lpm_capable;
};

/* QSPI PHY */
&qspi {
    #address-cells = <1>;
        #size-cells = <1><0>;
    };
};

/* DMA not used: Reduce error messages on linux.*/

&lpd_dma_chan1 {
 status = "okay";
    flash0: flash@0 {
        statuscompatible = "disabledjedec,spi-nor";
};
&lpd_dma_chan2 {
        statusreg = "disabled";
};
&lpd_dma_chan3 {
<0x0>;
        status#address-cells = "disabled"<1>;
};
&lpd_dma_chan4 {
    status = "disabled";
};
&lpd_dma_chan5 {
    status = "disabled";
};
&lpd_dma_chan6 {
    status = "disabled";
};
&lpd_dma_chan7 {
    status = "disabled";
};
&lpd_dma_chan8 {
    status = "disabled";
};

Kernel

Deactivate:

  • CONFIG_CPU_IDLE        (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ      (only needed to fix JTAG Debug issue)

Rootfs

Activate:

  • i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

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SI5338

Download  ClockBuilder Desktop for SI5338

  1. Install and start ClockBuilder
  2. Select SI5338
  3. Options → Open register map file
    Note: File location <design name>/misc/Si5338/RegisterMap.txt
  4. Modify settings
  5. Options → save C code header files
  6. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

 #size-cells = <1>;
    };
};


Kernel

Start with petalinux-config -c kernel

Changes:

  • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set (only needed to fix JTAG Debug issue)
  • CONFIG_EDAC_CORTEX_ARM64=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y (for web server app)

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

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  • SI5338 and SI5345 also Link to:


SI5338

File location <design name>/misc/Si5338/Si5338-*.slabtimeproj

General documentation how you work with these project will be available on Si5338


Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionAuthorsDescription

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modified-date
dateFormatyyyy-MM-dd

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current-version
prefixv.



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modified-user

  • 2018.3 release finished (include design reworks)
  • working in process

v.43John Hartfiel
  • Update Design files for 2GB variants
  • rebuilt petalinux for optional init script

v.41John Hartfiel
  • Update Design files for 2GB variants

v.40John Hartfiel
  • add notes to ES1

v.38John Hartfiel
  • 2018.2 release finished

v.34John Hartfiel
  • Design Files Update

v.29John Hartfiel
  • Design Files Update
2018-02-06v.27John Hartfiel
  • Design Files Update
2018-01-29v.26John Hartfiel
  • Update Known Issues
2018-01-24v.25John Hartfiel
  • Release 2017.4
2018-01-10v.24John Hartfiel
  • Update Known Issues
2017-12-20v.23John Hartfiel
  • Typo correction
  • Update HW Module Table Description
2017-11-21

v.19

John Hartfiel
  • Design Update
2017-11-20v.18John Hartfiel
  • Design Update
  • Add Variants with 128MB Flash
2017-11-13v.16John Hartfiel
  • Update Carrier sections
2017-11-06v.15John Hartfiel
  • Typo corrected
2017-10-23v.13John Hartfiel
  • Update Key Features section
  • Style Update Additional Software section
2017-10-19
v.9
John Hartfiel
  • Release 2017.2
2017-09-11v.1

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Initial release

All

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Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices

...