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Table of Contents

Table of Contents

Overview

The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ..TEP0003 is is a BEMF (Back Electromagnetic Field) based drive. It can be used in many low cost drives where no low speed operation is needed.

Refer to http://trenz.org/tec0850tep0003-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modues:

  • SoC/FPGA
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • Modules/ SoC FPGA
    • TE0808, TE807, TE0803,...

      Compatible with Digilent's Pmod interfaces

  • RAM/Storage
  • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension
  • On Board
    • 2x A2D Converters
    • 3x Current Sensors
    • 6x Power Stages
  • Interface
    • 2x Pmod Pin Headers (2x6 Pol)
  • Power 
    •  3.3V supply voltage from Pmods
  • Dimension
    • 40 mm x 40 mm

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorFigure_OV_BD
titleTExxxx TEP0003 block diagram


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Main Components

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Main Components

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Notes :

  • Picture of the PCB
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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorFigure_OV_MC
titleTExxxx TEP0003 main components


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  1. ...
  2. ...
  3. ...

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module
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  1. Pmod Pin Header, J1
  2. Pmod Pin Header, J2
  3. Synchronous DC/DC Converter, U7
  4. Power Stages, U1...U6
  5. Current Sensors, U18, U21, U46
  6. ADC, U22, U47
  7. Terminal Block, J3
  8. Terminal Block, J4
  9.  Low-Power Push-Pull Output Comparator, U9

Initial Delivery Stat

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Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


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titleInitial delivery state of programmable devices on the module

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Storage device name

...

Content

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Notes

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Quad SPI Flash

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Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.
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titleBoot process.

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MODE Signal State

Boot Mode
Scroll Title

Storage device name

Content

Notes

--


--

--


Configuration Signals

Note
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  • Overview of Boot Mode, Reset, Enables.
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titleReset process.
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Signal

B2BI/O

Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

Pmod Connectors

TEP0003 is equipped with two Pmod Connectors. FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title
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titleGeneral PL I/O to B2B connectors information

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FPGA Bank
Pin
B2B ConnectorI/O Signal CountVoltage LevelNotes

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JTAG access to the TExxxx SoM through B2B connector JMX.

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anchorTable_SIP_JTG
titleJTAG pins connection
SchematicNotes
Pmod, J1Pmod, J2
1PWM_CH0ADC_CH
2PWM_CH1ADC_SCK
3PWM_CH2ADC_CS
4-SENSOR_FAUL
5GNDGND
63.3V3.3V
7COMP_CH0ADC0_DO
8COMP_CH1ADC1_DO
9COMP_CH2-
10--
11GNDGND
123.3V3.3V


Terminal blocks

The TEP0002 is equipped with two Terminal Blocks J3 and J4.

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JTAG Signal

...

B2B Connector

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MIO Pins

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

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MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI
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titleMIOs pinsTerminal Blocks information

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Designator
MIO PinConnected toB2B
PinSchematicNotes
J31DRV_CH2ARK500-3
2DRV_CH1ARK500-3
3DRV_CH0ARK500-3
J41DC_INARK500-2
2GNDARK500-2
Notes


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

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titleOn board peripherals

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Chip/InterfaceDesignatorNotes

Quad SPI Flash Memory

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ADCU22, U47


Analog to Digital Converters

The TEP0003 has two ADCs, U22 and U47. 

U?? Pin
Scroll Title
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titleQuad SPI interface MIOs and pinsAnalog Digital Converter

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Pins
MIO PinSchematic
Connected to
ADC, U22ADC, U47Notes

...

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AVDD
5V
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titleI2C interface MIOs and pins
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MIO PinSchematicU? PinNotes
Scroll Title
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titleI2C Address for RTC
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MIO PinI2C AddressDesignatorNotes

...

5V
REF5V5V
AIN0+U18 (VIOUT)DC_IN
AIN0-GNDGND
AIN1+U21 (VIOUT)U46 (VIOUT)
AIN1-GNDGND
REFGNDGNDGND
DVDD3.3V3.3V
SCLKADC_SCKADC_SCKAccess via Pmod, J2
SDOADC1_DOADC0_DOAccess via Pmod, J2
CSADC_CSADC_CSAccess via Pmod, J2
CH_SELADC_CHADC_CHAccess via Pmod, J2
PDENGNDGND



Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

TEP0003 will be power supplied through 3.3V from Pmods, J1 and J2.

Power Consumption

Scroll Title
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titleI2C EEPROM interface MIOs and pins
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MIO PinSchematicU?? PinNotes
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anchorTable_OBPPWR_I2C_EEPROMPC
titleI2C address for EEPROMPower Consumption

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MIO
Power Input Pin
I2C AddressDesignatorNotes

...

Typical Current
3.3VTBD*


* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title
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titleOn-board LEDsPower Distribution


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DesignatorColorConnected toActive LevelNote

DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

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anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

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CAN Transceiver

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anchorTable_OBP_CAN
titleCAN Tranciever interface MIOs

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titleOsillators

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Power and Power-On Sequence

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hiddentrue
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

...

anchorTable_PWR_PC
titlePower Consumption

...

* TBD - To Be Determined

Power Distribution Dependencies

...

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titlePower Distribution
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Power-On Sequence

There is no specific power on sequence, after power on all electrical components will be enabled. 

Power Rails

Power-On Sequence

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anchorFigure_PWR_PS
titlePower Sequency
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Voltage Monitor Circuit

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anchorFigure_PWR_VMC
titleVoltage Monitor Circuit
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Power Rails

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anchorTable_PWR_PR
titleModule power rails.

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B2B Connector

JM1 Pin

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B2B Connector

JM2 Pin

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B2B Connector

JM3 Pin

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Bank Voltages

Scroll Title
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titleZynq SoC bank voltages.
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Bank          

Schematic Name

Voltage

Notes

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use "include page" macro and link to the general B2B connector page of the module series,

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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

PR
titleModule power rails.

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Power Rail Name

Pmod J1 Pin

Pmod J2 Pin

Notes
3.3V6,126,12

...



Technical Specifications

Absolute Maximum Ratings

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titlePS absolute maximum ratings

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SymbolsDescriptionMinMaxUnit
V
3.3VSupply Voltage-0.36.5
V
V
V
T_STGStorage Temperature-40105°C
VVVV