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  • Modules/ SoC FPGA

    • Compatible with Digilent's Pmod interfaces

  • RAM/Storage
  • On Board
    • 2x A2D Converters
    • 3x Current Sensors
    • 6x Power Stages
  • Interface
    • 2x Pmod Pin Header Headers (2x6 Pol)
  • Power 
    •  3.3V supply voltage from Pmods
  • Dimension
    • 40 mm x 40 mm

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Scroll Title
anchorFigure_OV_BD
titleTExxxx TEP0003 block diagram


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Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

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3.3V
PinSchematicNotes
Pmod, J1Pmod, J2
1PWM_CH0ADC_CH
2PWM_CH1ADC_SCK
3PWM_CH2ADC_CS
4-SENSOR_FAUL
5GNDGND
63.3V3.3V
7COMP_CH0ADC0_DO
8COMP_CH1ADC1_DO9COMP_CH2-10--11GNDGND123.3V
9COMP_CH2-
10--
11GNDGND
123.3V3.3V


Terminal blocks

The TEP0002 is equipped with two Terminal Blocks J3 and J4.

Scroll Title
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titleTerminal Blocks information

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DesignatorPinSchematicNotes
J31DRV_CH2ARK500-3
2DRV_CH1ARK500-3
3DRV_CH0ARK500-3
J41DC_INARK500-2
2GNDARK500-2


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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Scroll Title
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titlePS absolute maximum ratings

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SymbolsDescriptionMinMaxUnit
3.3VSupply Voltage-0.3.1536.455V
T_STGStorage Temperature-5540150105°C


Recommended Operating Conditions

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Scroll Title
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titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document
3.3V3.3034.32VSupplied from Pmod
T_OPR-4030+125105°CSee ARK500-3 and ARK500-2 Datasheet


Physical Dimensions

  • Module size: 40 mm × 40 mm.  Please download the assembly diagram for exact numbers.

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Scroll Title
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titleHardware Revision History

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DateRevisionChangesDocumentation Link
2018-07-1801
  • Initial Release
REV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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