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Table of Contents

Table of Contents

Overview

The Trenz Electronic TEP0003 is is a Pmod compatible motor driver board and good for developing BLCD or CD motor driving softwareBEMF (Back Electromagnetic Field) based drive. It can be used in many low cost drives where no low speed operation is needed.

Refer to http://trenz.org/tep0003-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modues:

  • SoC/FPGA
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • Modules/ SoC FPGA
    • Compatible with Digilent's Pmod interfaces

  • RAM/Storage
  • On Board
    • 2x A2D Converters
    • 3x Current Sensors
    • 6x Power Stages
  • Interface
    • 2x Pmod Pin Header Headers (2x6 Pol)
  • Power 
    •  3.3V supply voltage from Pmods
  • Dimension
    • 40 mm x 40 mm

Block Diagram

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add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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titleTExxxx TEP0003 block diagram


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Main Components

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  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .


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titleTExxxx TEP0003 main components


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  1. Pmod Pin Header, J1
  2. Pmod Pin Header, J2
  3. Synchronous DC/DC Converter, U7
  4. Power Stages, U1...U6
  5. Current Sensors, U18, U21, U46
  6. ADC, U22, U47
  7. Terminal Block, J3
  8. Terminal Block, J4
  9.  Low-Power Push-Pull Output Comparator, U9

Initial Delivery Stat

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Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

--


--

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Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Pmod Connectors

TEP0003 is equipped with two Pmod Connectors. 

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titleGeneral PL I/O to B2B connectors information

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PinSchematicNotes
Pmod, J1Pmod, J2Notes
1PWM_CH0ADC_CH
2PWM_CH1ADC_SCK
3PWM_CH2ADC_CS
4-SENSOR_FAUL
5GNDGND
63.3V3.3V
7COMP_CH0ADC0_DO
8COMP_CH1ADC1_DO
9COMP_CH2-
10--
11GNDGND
123.3V3.3V

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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titleOn board peripherals


Terminal blocks

The TEP0002 is equipped with two Terminal Blocks J3 and J4.

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titleTerminal Blocks information

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DesignatorPinSchematicNotes
J31DRV_CH2ARK500-3
2DRV_CH1ARK500-3
3DRV_CH0ARK500-3
J41DC_INARK500-2
2GNDARK500-2


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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Analog to Digital Converters

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titleAnalog Digital Converter

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Chip/InterfaceDesignatorPinsNotesSchematic
ADCNotesADC

Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

U22, U47


Analog to Digital Converters

The TEP0003 has two ADCs, U22 and U47. 

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PinsConnected to
ADC, U22ADC, U47Notes
AVDD5V5V
REF5V5V
AIN0+U18 (VIOUT)DC_IN
AIN0-GNDGND
AIN1+U21 (VIOUT)U46 (VIOUT)
AIN1-GNDGND
REFGNDGNDGND
DVDD3.3V3.3V
SCLKADC_SCKADC_SCKAccess via Pmod, J2
SDOADC1_DOADC0_DOAccess via Pmod, J2
CSADC_CSADC_CSAccess via Pmod, J2
CH_SELADC_CHADC_CHAccess via Pmod, J2
PDENGNDGND



Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

TEP0003 will be power supplied through 3.3V from Pmods, J1 and J2.

Power Consumption

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Power Input PinTypical Current
3.3VTBD*


* TBD - To Be Determined

Power Distribution Dependencies

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Power-On Sequence

There is no specific power on sequence, after power on all electrical components will be enabled. 

Power Rails

Power Supply

TEP0003 will be power supplied through 3.3V from Pmods.

Power Consumption

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* TBD - To Be Determined

Power Distribution Dependencies

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Power-On Sequence

There is no specific power on sequence, after power on all electrical components will be enabled. 

Power Rails

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titleModule power rails.

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Pmod J1 Pin

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Pmod J2 Pin

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Notes
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titleZynq SoC bank voltagesModule power rails.

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Power Rail Name

Pmod J1 Pin

Pmod J2 Pin

Notes
3.3V6,126,12

Bank          

Schematic Name

Voltage



Technical Specifications

Absolute Maximum Ratings

V
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SymbolsDescriptionMin
MaxUnit
3.3VSupply Voltage-0.36.5V
T_STGStorage Temperature-40105°C
MaxUnitVV


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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ParameterMinMaxUnitsReference Document
VSee ???? datasheets.VSee Xilinx ???? datasheet.°C
3.3V3.04.2VSupplied from Pmod
T_OPR-30+105°CSee ARK500-3 and ARK500-2 Datasheet
See Xilinx ???? datasheet.