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anchor	Table_SIP_B2B
title	General PL I/O to B2B connectors information

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Pin	Schematic		Notes
Pin	Pmod, J1	Pmod, J2	Notes
1	PWM_CH0	ADC_CH
2	PWM_CH1	ADC_SCK
3	PWM_CH2	ADC_CS
4	-	SENSOR_FAUL
5	GND	GND
6	3.3V	3.3V
7	COMP_CH0	ADC0_DO
8	COMP_CH1	ADC1_DO
9	COMP_CH2	-
10	-	-
11	GND	GND
12	3.3V	3.3V

Terminal blocks

The TEP0002 is equipped with two Terminal Blocks J3 and J4.

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anchor	Table_SIP_TerBlk
title	Terminal Blocks information

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Designator	Pin	Schematic	Notes
J3	1	DRV_CH2	ARK500-3
	2	DRV_CH1	ARK500-3
	3	DRV_CH0	ARK500-3
J4	1	DC_IN	ARK500-2
J4	2	GND	ARK500-2

On-board Peripherals

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id	Comments

Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

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anchor	Table_RH_HRH
title	Hardware Revision History

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Date	Revision	Changes	Documentation Link
2018-07-18	01	Initial Release	REV01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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