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Important General Note:
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Table of Contents
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Overview
The Trenz Electronic TE0835 is an extended-grade module based on Xilinx UltraScale+ RFSoC.
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Notes :
short description of the PCB
Short Link of the wiki resources reference:
Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects
Key Features
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'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options
Key Features' must be split into 6 main groups for modules and mainboards:
- SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- size:*
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- Low Power DDR4 on PS
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- 4 cm x 5 cm
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier:
- Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- E.g. SDRAM, SPI
- On Board
- E.g. CPLD, PLL
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
- SoC/FPGA
- Xilinx UltraScale+ RFSoC (XCZU25DR-1FFVE1156E)
- Package: E1156
- Speed: -1 (slowest)
- Temperature: Extended (0 to +100 °C)
- Xilinx UltraScale+ RFSoC (XCZU25DR-1FFVE1156E)
- RAM/Storage
- 4x 8Gb DDR4
- 2x 512Mb SPI Flash
- 2k I2C EEPROM
- On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- 3x Oscillators
- Interface
- 2x Samtec ST5 (2x80 pol) Board to Board Connectors
- Power
- 5V Input Supply Voltage
- Dimension
- 90 x 65 mm
Block Diagram
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add drawIO object here.
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For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" . |
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anchor | Figure_OV_BD |
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title | TE0835 block diagram |
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Main Components
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Notes :
- Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" . |
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anchor | Figure_OV_MC |
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title | TE0835 main components |
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- Xilinx UltraScale+ RFSoC XCZU25DR, U1
- 8Gb DDR4 SDRAM, U2,U3,U5,U9
- Voltage Regulators, U4,U6,U7
- Programmable Glock Generator, U15
- Lattice MachXO2 CPLD, U31
- Dual SPI Flash, U24-U25
- USB2.0 Transceiver, U11
- Pin Header 3x1, J3 (not Soldered)
- Gigabit Ethernet Transceiver, U20
- EEPROM, U23
- B2B Connector, J2
- B2B Connector, J1
Initial Delivery State
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id | Comments |
Notes :
Only components like EEPROM, QSPI flash can be initialized by default at manufacture.
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Storage device name
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Content
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Notes
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2x SPI Flash
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Configuration Signals
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Configuration must be set through CPLD,U31 by setting MODE0...3 signals.
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anchor | Table_OV_BP |
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title | Boot process. |
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MODE[0:3]
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0000
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PS_JTAG
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anchor | Table_OV_RST |
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title | Reset process. |
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Signal
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RESETN
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Signals, Interfaces and Pins
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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MIO Pins
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id | Comments |
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
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SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
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anchor | Table_OBP_MIOs |
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title | MIOs pins |
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UART_TX, UART_RX
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Test Points
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id | Comments |
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
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B2B, J1
CPLD, U31
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B2B, J1
CPLD, U31
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B2B, J1
CPLD, U31
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B2B, J1
CPLD, U31
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B2B, J1
CPLD, U31
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IO_L1P_AD15P_88,
O_L4N_AD12N_88
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EEPROM,U23
FPGA Bank 501, U1
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Notes :
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
The TE0835 is a Dual SPI Flash module equipped with two SPI Flash U24, U25 connecfted to PSMIO FPGA bank 500.
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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B2B Connector
JM1 Pin
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B2B Connector
JM2 Pin
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B2B Connector
JM3 Pin
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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Bank
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Voltage
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title | Hardware Revision History |
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