Page History

Custom_table_size_100

Page properties

hidden	true
id	Comments

Template Revision 2.15

Template Change history:

2.14 to 2.15
- add excerpt macro to key features
2.13 to 2.14
- add fix table of content
- add table size as macro
2.12 to 2.13
- Changed controller Signals section

Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"

...

HTML

<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>

...

hidden	true
id	Comments

Important General Note:

...

Page properties

hidden	true
id	Comments

Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
Scroll Title
anchor Table_tablename
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
style
widths
sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

Page properties

hidden	true
id	Comments

-----------------------------------------------------------------------

Page properties

hidden	true
id	Comments

Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Scroll pdf ignore

Table of Contents

Table of Contents

Overview

...

Zynq UltraScale+ RFSoC. The module is equipped with 4x 8Gb DDR4 SDRAM Memory, 2x 512Mb SPI Flash Memory, USB2.0, Ethernet Transceiver and 2x Samtec Razor Beam Borard to Board (B2B) Connectors. The system controller CPLD is provided by Lattice MachXO2.

The Zynq UltraScale+ RFSoC family integrates key subsystems for multiband, multi-mode cellular radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bitquad-core Arm Cortex-A53 and dual-core Arm Cortex-R5 based processing system.

Refer to http://trenz.org/te0835-info for the current online version of this manual and other available documentation.

Page properties

hidden	true
id	Comments

Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

Page properties

hidden	true
id	Comments

Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features' must be split into 6 main groups for modules and mainboards:

SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
RAM/Storage
- Low Power DDR4 on PS
  - Data width: 32bit
  - Size: def. 2GB*
  - Speed:***
- eMMC
  - Data width: 8Bit
  - size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
  - Data width: 8bit
  - size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
  - size:*
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
Dimension
- 4 cm x 5 cm
Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination

Key Features' must be split into 6 main groups for carrier:

Modules
- TE0808

...

E.g. SDRAM, SPI

...

E.g. CPLD, PLL

...

E.g. ETH, USB, B2B, Display port

...

E.g. Input supply voltage

...

Lattice MachXO2 CPLD
Programmable Clock Generator
3x Oscillators

...

2x Samtec ST5 (2x80 pol) Board to Board Connectors

...

5V Input Supply Voltage

...

90 x 65 mm

- E.g. CPLD, PLL
Interface
- E.g. ETH, USB, B2B, Display port
Power
- E.g. Input supply voltage
Dimension

Excerpt

SoC/FPGA
- Package: FFVE1156, FSVE1156
- Device: ZU25, ZU27, ZU28, ZU43, ZU47, ZU48*
- Engine: DR
- Speed: -1, -L1, -2, -L2
- Temperature: E, I*
RAM/Storage
- 4x 8Gb DDR4
- 2x 512Mb SPI Flash
- 2k I²C EEPROM
On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- USB2.0 Transceiver
- Gigabit Ethernet Transceiver
- 3x Oscillators
- 4x User LEDs
Interface
- 2x Samtec Razor Beam ST5 (2x80 pol) Board to Board Connectors
Power
- 5V Input Supply Voltage
Dimension
- 90 x 65 mm
Note
- * Different packages, speed and temperature range are available on assembly options

Block Diagram

...

hidden	true
id	Comments

add drawIO object here.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

...

anchor	Figure_OV_BD
title	TE0835 block diagram

...

Scroll Only
Image Removed

...

Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

...

2x SPI Flash

...

Configuration Signals

...

Image Removed

Xilinx UltraScale+ RFSoC XCZU25DR, U1
8Gb DDR4 SDRAM, U2,U3,U5,U9
Voltage Regulators, U4,U6,U7
Programmable Glock Generator, U15
Lattice MachXO2 CPLD, U31
Dual SPI Flash, U24-U25
USB2.0 Transceiver, U11
Pin Header 3x1, J3 (not Soldered)
Gigabit Ethernet Transceiver, U20
EEPROM, U23
B2B Connector, J2
B2B Connector, J1

Initial Delivery State

Page properties

hidden	true
id	Comments

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

...

anchor	Table_OV_IDS
title	Initial delivery state of programmable devices on the module

...

Storage device name

...

Content

...

Notes


Image Added

Main Components

Page properties

hidden	true
id	Comments

Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title	TE0835 main components

Scroll Ignore

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramDisplayName
lbox	true
revision	21
diagramName	TE0835_OV_MC
simpleViewer	false
width	639
links	auto
tbstyle	hidden
diagramWidth	641

Scroll Only
Image Added

Xilinx UltraScale+ RFSoC, U1
8Gb DDR4 SDRAM, U2,U3,U5,U9
Voltage Regulators, U4,U6,U7
User Red LEDs, D2...5
Error/Status Red LEDs, D6...7
Programmable Glock Generator, U15
Lattice MachXO2 CPLD, U31
Dual SPI Flash, U24-U25
USB2.0 Transceiver, U11
Pin Header 3x1, J3 (not Soldered)
Green LED, D1
Gigabit Ethernet Transceiver, U20
EEPROM, U23
B2B Connectors, J1
B2B Connectors, J2

Initial Delivery State

...

Overview of Boot Mode, Reset, Enables.

...

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title

anchor	Table_OV_

...

MODE[0:3]

...

0000

...

PS_JTAG

...

	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
2x SPI Flash	Not Programmed
System Controller CPLD	Programmed
EEPROM	Not Programmed
4x DDR4 SDRAM	Not Programmed
Programmable Clock Generator	Not Programmed

Configuration Signals

Page properties

hidden	true
id	Comments

Overview of Boot Mode, Reset, Enables.

Configuration must be set through CPLD,U31 by setting MODE0...3 signals.

Scroll Title

anchor	Table_OV_BP
title	Boot process.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MODE[3:0]	Boot Mode	Note
0000	PS_JTAG	Refer to CPLD Page
0001	Quad SPI Flash	Refer to CPLD Page
0101	SD Card	Refer to CPLD Page

The reset pin is active low.

Scroll Title

anchor	Table_OV_RST
title	Reset process.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Signal	B2B	I/O	Note
RESETN	J1-36	Input	Pulled up to 3.3V_CPLD

Signals, Interfaces and Pins

Page properties

hidden	true
id	Comments

Notes :

For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- SD
- USB
- ETH
- FMC
- ...
For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title

anchor	Table_SIP_B2B
title	General PL I/O to B2B connectors information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

FPGA Bank	B2B Connector	Number of I/Os	Voltage Level	Notes
Bank 500	J1	12x Single Ended	1.8V	MIO14...25
Bank 501	J1	20x Single Ended	1.8V	MIO26...51
Bank 505	J1	18x Single Ended, 9x Differential pairs	0.85V	EXT_CLKIN_PSMGT, RX/TX0...3
Bank 128	J1

...

3
Bank 65	J2	24x Single Ended, 12x Differential pairs	1.8V	HP Bank
Bank 88	J2	16x Single Ended, 8x Differential pairs	3.3V	HD Bank
ADC	J2	16x Single Ended, 8x Differential pairs 4x Differential Clocks	Variable
DAC	J2	16x Single Ended, 8x Differential pairs 3x Differential Clocks	Variable

JTAG Interface

JTAG access to the Xilinx UltraScale+ MPSoC is through B2B connector JM1. JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. When the CPLD_JTAGEN is 0 or off, it provides FPGA access and when it is 1 or ON, it provides CPLD access.

Scroll Title

anchor	Table_SIP_JTG
title	JTAG pins connection

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

JTAG Signal	B2B Connector
JTAG_TMS	J1-24
JTAG_TDI	J1-20
JTAG_TDO	J1-18
JTAG_TCK	J1-22

MIO Pins

Page properties

hidden	true
id	Comments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO Pin

Connected to

B2B

Notes

MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2

QSPI

Scroll Title

anchor	Table_OBP_MIOs
title	MIOs pins

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin	Connected to	B2B	Notes
MIO0...12	SPI FLash, U24-U25	-	Dual SPI FLash
MIO13	LED Green, D1	-	3.3V_CPLD
MIO14...25	FPGA Bank 500,U1	J1	PSMIO
MIO26...27	FPGA Bank 501,U1	J1	PSMIO
MIO28...29	CPLD, U31	-	UART_TX, UART_RX
MIO30...31	FPGA Bank 501, U1	J1	PSMIO
MIO32...33	EEPROM,U23	-	I2C_SCL, I2C_SDA
MIO34...35	FPGA Bank 501,U1	J1	PSMIO
MIO36	Gigabit ETH, U20	-	ETH_RST
MIO37	USB2.0, U11	-	USB_RST
MIO38...51	FPGA Bank 501, U1	J1	PSMIO
MIO52...62	USB2.0, U11	-	USB
MIO63...77	Gigabit ETH, U20	-	ETH

Test Points

Page properties

hidden	true
id	Comments

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test Point	Signal	B2B	Notes
10	PWR_PL_OK	J2-120

Scroll Title

anchor	Table_SIP_TPs
title	Test Points Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Test Point	Signal	Connected to	Notes
TP1	CLKOUT	Voltage Regulator, U7
TP2	PLL_RSTN	Programmable Clock Generator, U15

...

U10

TP20

3.3V_CPLD

CPLD, U31

B2B, J1

T21

CPLD_JT AGEN

B2B, J1

CPLD, U31

On-board Peripherals

Page properties

hidden	true
id	Comments

Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

Page properties

hidden	true
id	Comments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Scroll Title

anchor	Table_OBP
title	On board peripherals

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Chip/Interface	Designator	Notes

...

QSPI Flash	U24, U25
DDR4 SDRAM	U2, U3, U5, U9
CPLD	U31
USB2.0	U11
Gigabit Ethernet	U20
Programmable Clock Generator	U15
EEPROM	U22
Oscillators	U14, U21, U12
LEDs	D0...7

Quad SPI Flash Memory

Page properties

hidden	true
id	Comments

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TE0835 is a Dual SPI Flash module equipped with two SPI Flash U24, U25 connecfted to PSMIO FPGA bank 500.

Scroll Title

anchor	Table_OBP_SPI
title	Quad SPI interface MIOs and pins

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin	Schematic	U24 Pin	U25 Pin
MIO0	MIO0_QSPI	CLK	-
MIO1	MIO1_QSPI	DO	-
MIO2	MIO2_QSPI	nWP	-
MIO3	MIO3_QSPI	nHOLD	-
MIO4	MIO4_QSPI	DI	-
MIO5	MIO5_QSPI	nCS	-
MIO7	MIO5_QSPI	-	nCS
MIO8	MIO5_QSPI	-	DI
MIO9	MIO5_QSPI	-	DO
MIO10	MIO5_QSPI	-	nWP
MIO11	MIO5_QSPI	-	nHOLD

...

System Controller CPLD

The System Controller CPLD (U31) is provided by Lattice Semiconductor LCMXO2-460HC. The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG / UART and I²C between the on-board peripherals and the attached module are by-passed, forwarded and controlled by the System Controller CPLD.

...


MIO12	MIO5_QSPI	-	CLK

System Controller CPLD

The System Controller CPLD (U31) is provided by Lattice Semiconductor LCMXO2-460HC. The CPLD provides JTAG routing, boot mode, User IOs, LEDs, firmware and power management access. For more information please refer to the TE0835 CPLD page.

Scroll Title

anchor	Table_OBP_USB
title	USB2.0 interface connections and pins

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic/Pin	Connected to	Description	Note
MODE0...3	FPGA Bank 503, U1	Boot Mode
POR_B	FPGA Bank 503, U1	Programming Status	Pulled up
PORG_B	FPGA Bank 503, U1	Programming Status	Pulled up
INIT_B	FPGA Bank 503, U1	Configuration initialization	Pulled up
DONE	FPGA Bank 503, U1	Configuration Done Status	Pulled up
F_TCK	FPGA Bank 503, U1	FPGA JTAG
F_TDI	FPGA Bank 503, U1	FPGA JTAG
F_TMS	FPGA Bank 503, U1	FPGA JTAG
F_TDO	FPGA Bank 503, U1	FPGA JTAG
JTAG_TDO	B2B, J1	CPLD JTAG
JTAG_TMS	B2B, J1	CPLD JTAG
JTAG_TDI	B2B, J1	CPLD JTAG
JTAG_TCK	B2B, J1	CPLD JTAG
CPLD_JTAGEN	B2B, J1	CPLD JTAG Enable
CPLDIO0...3	B2B, J1	CPLD IOs
RESETN	B2B, J1	Reset
MIO13	LED Green, D1	3.3V_CPLD
MIO28	FPGA Bank 501, U1	UART_TX
MIO29	FPGA Bank 501, U1	UART_RX
FPGA_IO0...1	FPGA Bank 65, U1	IOs
EN_PS_PL	Voltage Regulators, U6, U7, U29	PS/PL Enable Signals	Pulled Down
EN_GR1	Voltage Regulators, U19, U27, U28	MGTAVTT, PSLL	Pulled Down
EN_GR2	Voltage Regulators, U38, U18, U38	PS_MGTRAVTT, 3.3, DDR2.5V	Pulled Down
EN_RF_ADC	Voltage Regulators, U8	Enable ADC	Pulled Down
PG_RF_DAC	Voltage Regulators, U17	ADC Power Good Status	Pulled Down
PG_PS_PL	Voltage Regulators, U6, U7, U29	PS/PL Power Good Status	Pulled Down
EN_RF_DAC	Voltage Regulators, U13	Enable DAC	Pulled Down
PG_RF_DAC	Voltage Regulators, U10	DAC Power Good Status	Pulled Down

USB2.0

The TE0835 is equipped with a USB2.0, U11.

Scroll Title

anchor	Table_OBP_USB
title	USB2.0 interface connections and pins

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

U11 Pin	Schematic	Connected to
RESETB	USB0_RST	FPGA Bank 501, U1
VDDIO	1.8V	1.8V
CPEN	USB0_CPE	B2B, J1
VBUS	USB0_VBUS	B2B, J1
ID	USB0_ID	B2B, J1
DP	USB0_D_P	B2B, J1
DM	USB0_D_N	B2B, J1
REFCLK	USB_CLK	Oschillator, U12
STP	USB0_STP	FPGA Bank 502, U1
NXT	USB0_NXT	FPGA Bank 502, U1
DIR	USB0_DIR	FPGA Bank 502, U1
CLKOUT	USB_CLK	Oschillator, U12
DATA0...7	USB0_DATA0...8	FPGA Bank 502, U1

Ethernet

The module TE0835 is equipped with a Gigabit Ethernet Transceiver, U20.

Scroll Title

anchor	Table_OBP_ETH
title	Ethernet connections

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

U20 Pin	Signal Name	Connected to	Signal Description
MDIO	ETH_MDIO	FPGA Bank 502, U1	Data Management
MDC	ETH_MDC	FPGA Bank 502, U1	Data Management clock reference for the serial interface
TX_CLK	ETH_TXCK	FPGA Bank 502, U1	Transmit Clock
TX_CTRL	ETH_TXCTL	FPGA Bank 502, U1	Transmit Control
TXD0...3	ETH_TXD0...3	FPGA Bank 502, U1	Transmit Data
RX_CLK	ETH_RXCK	FPGA Bank 502, U1	Receive Clock
RX_CTRL	ETH_RXCTL	FPGA Bank 502, U1	Receive Control
RXD0...3	ETH_RXD0...3	FPGA Bank 502, U1	Receive Data
RESETn	ETH_RST	FPGA Bank 501, U1	Ethernet reset, Active low.
XTAL_IN	ETH_XTAL_IN	Oscillator, U21	Reference Clock
MDI0...3	PHY_MDI0...3	B2B, J1	Media Dependent Interface 0...3
LED0...1	PHY_LED0...1	B2B, J1	LED output
LED/INT	PHY_LED2	B2B, J1	LED interrupt

EEPROM

The module TE0835 has an EEPROM IC (U23) connected to PSMIO FPGA Bank 501.

Scroll Title

anchor	Table_OBP_EEP
title	I2C EEPROM interface MIOs and pins

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin	Schematic	U23 Pin	Notes
MIO32	MIO32_I2C1_SCL	SCL
MIO33	MIO33_I2C1_SDA	SDA

Scroll Title

anchor	Table_OBP_I2C_EEPROM
title	I2C address for EEPROM

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin	I2C Address	Designator	Notes
MIO32...33	0xA1	U23

LEDs

Scroll Title

anchor	Table_OBP_LED
title	On-board LEDs

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Designator	Color	Connected to	Active Level	Note
D1	Green	MIO13	Active High	3.3V CPLD
D2...5	Red	DBG_LED0...3	Active

...

Low	User LED
D6	Red	ERR_OUT	Active High
D7	Red	ERR_STATUS	Active High

DDR4 SDRAM

Page properties

hidden	true
id	Comments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0835 SoM has 4x 1 Gigabyte volatile DDR4 SDRAM IC for storing user application code and data.

Part number: K4A8G165WB
Supply voltage: 1.2 V
Speed: 2400 Mbps
Temperature: -40 ~ 95 °C

Clock Sources

Scroll Title

title
anchor	Table_OBP_CLK

...

Oscillators

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Designator	Description	Frequency
U14, U21	MEMS Oscillator	25MHz
U22	MEMS Oscillator	33.33 MHz
Y1	Crystal Oscillator	54 MHz
U12	MEMS Oscillator	52MHz
U15	Programmable Clock Generator	Variable

Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator on-board (U10) in order to generate reference clocks for the module. Programming can be done using I²C via PIN header J3. The I²C Address is 0x69.

Scroll Title

anchor	Table_OBP_PCLK
title	Programmable Clock Generator Inputs and Outputs

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

U15 Pin	Signal	Connected to	Direction	Note
IN0	IN0_P	Oscillator, U14	Input
IN1	-	N.C	-
IN2	EXT_CLK_IN1	B2B,J2	Input
IN3	-	N.C
nRST	PLL_RSTN	FPGA Bank 65,U1	Input
SCL	MIO32_I2C1_SCL	Pin Header, J3	Input	I2C
SDA	MIO33_I2C1_SDA	Pin Header,

...

Clock
OUT6	B128_CLK0	FPGA Bank 128,U1	Output
OUT7	B129_CLK0	FPGA Bank 129,U1	Output
OUT8	CLK8	FPGA Bank 65,U1	Output
OUT9	PSMGT_100MHZ	FPGA Bank 505,U1	Output
OUT9A	CLK0A_100MHZ	B2B, J1	Output

Power and Power-On Sequence

Page properties

hidden	true
id	Comments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of 2.5A for system startup is recommended.

Power Consumption

Scroll Title

anchor	Table_PWR_PC
title	Power Consumption

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Input Pin	Typical Current
VIN (5V)	TBD*

* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title

anchor	Figure_PWR_PD
title	Power Distribution

Scroll Ignore

draw.io Diagram

revision
border	false
viewerToolbar	true

fitWindow	false
diagramDisplayName
lbox	true

...

15
diagramName	TE0835_PWR_PD
simpleViewer	false
width	639
links	auto
tbstyle	hidden
diagramWidth	641

Scroll Only
Image Modified

Power-On Sequence

Scroll Title

anchor	Figure_PWR_PS
title	Power Sequency

Scroll Ignore

draw.io Diagram

revision
border	false
viewerToolbar	true

fitWindow	false
diagramDisplayName
lbox	true

...

8
diagramName	TE0835_PWR_PS
simpleViewer	false
width	639
links	auto
tbstyle	hidden
diagramWidth	641

Scroll Only
Image Modified

Power Rails

Scroll Title

anchor	Table_PWR_PR
title	Module power rails.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name

B2B Connector

...

B2B Connector

B2B J2 Pin	Direction	Notes
VIN	1,2,3,4,5,6,8	-	Input
PSBATT	14	-	Input
3.3V_CPLD	16	-	Output

Bank Voltages

Scroll Title

anchor	Table_PWR_BV
title	Zynq SoC bank voltages.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Bank	Schematic Name	Voltage
Bank 65 HP	VCCO_65	1.8V
Bank 503 PSCONFIG	VCCO_PSIO3_503	1.8V
Bank 88 HD	VCCO_88	3.3V

...


Bank 505 PSGTR	PS_MGTRAVCC	0.85V

Board to Board Connectors

Page properties

hidden	true
id	Comments

This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page

...

The TE0835 has two Samtec Razor Beam on the bottom side.

...

9 SoM SS5/ST5 B2B Connectors

Technical Specifications

Absolute Maximum Ratings

Scroll Title

anchor	Table_TS_AMR
title	PS absolute maximum ratings

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Symbols	Description	Min	Max	Unit
VIN	Input Supply Voltage	0	5	V
T_STG	Storage Temperature	-40

...

95

°C

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Scroll Title

anchor	Table_TS_ROC
title	Recommended operating conditions.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Parameter	Min	Max	Units	Reference Document
VIN	4.5	5.5	V	See Schematic

...

see USB3320 Datasheet

Physical Dimensions

Module size: 90 mm × 65 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 7 mm.

PCB thickness: 1.65 mm.

Page properties

hidden	true
id	Comments

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_TS_PD
title	Physical Dimension

Scroll Ignore

draw.io Diagram

revision
border	false
viewerToolbar	true

fitWindow	false
diagramDisplayName
lbox	true

...

4
diagramName	TE0835_TS_PD
simpleViewer	false
width	639
links	auto
tbstyle	hidden
diagramWidth	640

Scroll Only

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Image Modified

Currently Offered Variants

Page properties

hidden	true
id	Comments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

Scroll Title

anchor	Table_VCP_SO
title	Trenz Electronic Shop Overview

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Trenz shop TE0835 overview page
English page	German page

Revision History

Hardware Revision History

Page properties

hidden	true
id	Comments

Set correct links to download arrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD

Scroll Title

anchor	Table_RH_HRH
title	Hardware Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default

...


style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date

Revision

Changes

Documentation Link

2019-11-05

REV01

Initial Release

REV01

2020-06-17

REV02

1. Added a VRP resistor on bank 65;

2. LDO U33 is changed on ADP7102ACPZ;

3. Signal FPGA IO0 is connected on AE18 pin of FPGA;

4. Signal DBG_LED3 is connected on AD18 pin of FPGA;

5. Signal MIO13_25 connected to J1 pin 33 instead MIO25.

6. Resistor R84 is removed;

7. LED D1 moved on edge of PCB;

8. Added THT testpoints J4 on CPLD_JTAGEN, R76 was removed;

9. Signals B49_XX_X are renamed in B88_XX_X;

10. C241 is changed on 1nF;

11. Length of CLK signals on RFADC and RFDAC are adjusted;

12. Wrong connection on U8 is fixed (PCB);

13. Wrong connection PGOOD1 pin of U7 is fixed;

14. R17 is changed from 35,5K to 33K for VCC_PL_PS correction.

REV02

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Scroll Title

anchor	Figure_RV_HRN
title	Board hardware revision number.

Scroll Ignore

|

draw.io Diagram

revision
border	false
viewerToolbar	true

fitWindow	false
diagramDisplayName
lbox	true

...

9
diagramName	TE0835_RV_HRN
simpleViewer	false
width	200
links	auto
tbstyle	hidden
diagramWidth	198

Scroll Only
Image Modified

Document Change History

Page properties

hidden	true
id	Comments

Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

Scroll Title

anchor	Table_RH_DCH
title	Document change history.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date

Revision

Contributor

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

Page info

infoType	Current version
prefix	v.
type	Flat
showVersions	false

Page info

infoType	Modified by
type	Flat
showVersions	false

...

Bugfix Overview Picture

2021-12-21

v.58

John Hartfiel

Bugfix B2B section
Replace GTH with GTY

2021-05-28

v.55

John Hartfiel

Style update
Bugfix PDF Link
Key features update

2020-11-23

v.51

Pedram Babakhani

Update to REV02

--

all

Page info

infoType	Modified users
type	Flat
showVersions	false

--

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

Custom_fix_page_content

Scroll pdf ignore

Table of Contents

Table of Contents

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 25

New Version Current

Key

Overview

Overview

Key Features

Block Diagram

Block Diagram

Page propertieshiddentrueidComments

Configuration Signals

Initial Delivery State

Main Components

Initial Delivery State

Configuration Signals

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

JTAG Interface

MIO Pins

Test Points

On-board Peripherals

Quad SPI Flash Memory

System Controller CPLD

System Controller CPLD

USB2.0

Ethernet

EEPROM

LEDs

DDR4 SDRAM

Clock Sources

Programmable Clock Generator

Power and Power-On Sequence

Power Supply

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Power Rails

Bank Voltages

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Page properties
hidden true
id Comments