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Add Connections via clicking into the circle marked with a red rectangle in th picture above.
hps_0 - h2f_reset     →          clk_0 - clk_in_reset
clk_0 - clk                 →          hps_0 - f2h_sdram0_data

The HPS is nearly configures, at last apply some autofunctions:Before Generating HDL
System  →  Assign Base Addresses
System  →  Assign Interrupt Numbers
System  →  Assign Custom Instruction Opcodes
System  →  Create Global Reset Network

The Hardware Description language file is obtained by pressing Generate HDL in the bottom right corner of the
window. A new window opens, forcing to save the design. Name the file, the guide designates the file
PlatformEditorHPS.qsys .A new window opens, - Generation . In this window under Synthesis, selectvia select via Dropdown Menu in which
Hardware Language your HDL will be created, Verilog or VHDL, and check Create block symbole file (.bsf) .

Press Generate HDL  →  Setup of window Generation  →  Generate
  →   Window opens for saving press Save  →  Name the save and press save
Saving window opens → press close - Message: in the bottom left Generate and the saving dialogue opens, reminding to save the design. Name the file, this guide designates the file PlatformEditorHPS.qsys , press Save and wait until the design is saved. The window shows the
message - Save System: Completed successfully
Another .

Press Close and immediately a new window opens - Generate → press close - Message: Generate: completed with warnings, in it press Generate and wait for the
message - Generation: Completed successfully - to show up, press Close to shut the window down.

Close the Close Plattform Designer by pressing Finish.

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Löschen!!!!------------------------------------

Bottom right corner  →  Hit Generate HDL test
A new window opens, forcing to save the design. Give the file a name e.g. PlatformEditorHPS.qsys .
New window opens, under Synthesis, select which Hardware Language you prever Verilog ↔ VHDL
( Check - Create block symbole file (.bsf)
Click Generate and wait → Must be "Save System: completed successfully"

Hit close, Generate HDl window closes

Hit Finish, Plattform Editor window closes

Löschen!!!!------------------------------------ENDE

FRAGE: Enable MPU Interrupts auswählen, dann muss das verbunden werden oder Exportiert, wohin / womit?

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In Project Navigator use the Drop-down Menu for changing from Hierarchy to Files and right click onto the file to set it on top

TCL script loßlassen
Tools  →  TCL Scripts ...
New window  -  TCL Scripts - opens, select
Project1  →  PlatformEditorHPS  →  synthesis  →  submodules  →  hps_sdram_p0_pin_assignments.tcl
Click Run

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