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Tab SDRAM - Subtask - Memory Parameters:
Memory device speed grade: 800.0 MHz
Total interface width: 32
Row Address width: 16
Column Address width: 10

Memory Initialization Options
Memory CAS latency setting: 5
ODT Rtt nominal value: RZQ/6
Memory write CAS latency settings: 5

Tab SDRAM - Subtask - Memory Timing:
tIS (base): 180 ps      tIH (base): 140 ps     tDS (base) 30 ps     tDH (base):     65 ps    
tDQSQ: 100 ps          ps     tQH 0.38 cycles     cycles     tDQSCK_ 225 ps
tDQSS: 0.27 cycles    tQSH: 0.4 cycles       tDSH:0.18 cycles     tDSS: 0.18 cycles
cycles     tINIT: 500 us     tMRD (tMRW): 4 cycles    
tRAS: 35.0 ns     tRCD: 13.75 ns     tRP: 13.75 ns     tREFI (tREFIab): 7.8 us     tRFC (tRFCab): 350.0 ns     tWR: 15.0 ns
tWTR: 4 cycles   tFAW: 40 ns         tRRD: 12.0 ns     tRTP: 12.0 n

Tab SDRAM - Subtask - Board Settings:

Board Skews
Maximum CK delay to DIMM/device: 0.03
Maximum DQA delay to DIMM/device: 0.02
Minimum delay between CK and DQS: 0.09
Maximum delay between CK and DQS: 0.16
Maximum skew within DQS group: 0.01
Maximum skew between DQS groups: 0.08

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Click Finish in the bottom left to close the window - Arria V/Cyclone V Hard Processor System - hps_0 .
To change or correct these parameters later, (double) click onto the IP cores top entry in the tab System Contents.

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Add Connections via clicking into the circle marked with a red rectangle in th picture above.
hps_0 - h2f_reset     →          clk_0 - clk_in_reset
clk_0 - clk                 clk                →          hps_0 - f2h_sdram0_data

The HPS is nearly configures, at last apply some autofunctionsauto functions:
System  →  Assign Base Addresses
System  →  Assign Interrupt Numbers
System  →  Assign Custom Instruction Opcodes
System  →  Create Global Reset Network

The Hardware Description language file is obtained by pressing Generate HDL in the bottom right corner of the
window. A new window opens, - Generation . In this window under Synthesis, select via Dropdown Menu in which
Hardware Language your HDL will be created, Verilog or VHDL, and check Create block symbole file (.bsf) and 
uncheck Create timing and resource estimate... .

Press in the bottom left Generate and the saving dialogue opens, reminding to save the design. Name the file, this
guide designates the file PlatformEditorHPS.qsys , press Save and wait until the design is saved. The window shows
the
message - Save System: Completed successfully.

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