Download PDF version of this document.

Overview

The Trenz Electronic TE0865 is a high-performance MPSoC module integrating a Xilinx Zynq UltraScale+ ZU17EG (other assembly options for the FPGA are available), up to 8 GByte DDR4 SDRAM with ECC on PS, up to 8 GByte DDR4 SDRAM on PL, 256 MByte Flash memory for configuration and operation, Gigabit Ethernet PHY, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections. 

The prototype configuration of TE0865 will be available with many configuration options available that you can customize to meet your specific needs.

Temperature range depends on assembly version, for more information see section Recommended Operating Condition. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Refer to http://trenz.org/te0865-info for the current online version of this manual and other available documentation.

Key Features

  • SoC/FPGA
    • Package: C1760
    • Device: ZU11, ZU17, ZU19*
    • Engine: EG*
    • Speed: -1, -2,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • DDR4 on PS with ECC
      • Data width: 64 bit
      • Size: def. 4GB*
      • Speed: 2400 (Gb/s) ***
    • DDR4 on PL
      • Data width: 64 bit
      • Size: def. 4GB*
      • Speed: max 2666 (Gb/s) ***
    •  eMMC
      • Data width: 8 Bit
      • size: def. 8 GB *
    • Dual QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 64MB *
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Intel Max 10 FPGA as CPLD
    • 6x MEMS Oscillator
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3340C)
  • Interface
    • Trenz 7.5 x10 SoM 4x B2B Connector (Samtec ADM6) socket:
      • IO MIO:  27x SE
      • IO HP:   256x SE / 126x DIFF
      • IO HD:  102x SE / 48x DIFF
      • MGT
        • GTY: 16x MGT and 3x CLK
        • GTH: 32x and 8x CLK
        • GTR: 4x and 2x CLK
  • Power
    • 12V input supply voltage
    • Variable Bank IO Power Input
  • Dimension
    • 7.5 cm x 10 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination

Block Diagram

TE0865 block diagram

Main Components

TE0865 main components
  1. ZYNQ Ultrascale+ MPSoC FPGA, U30
  2. PL DDR4 SDRAM, U9, U10, U28, U29
  3. PS DDR4 SDRAM, U5...U8, U11
  4. Intel MAX 10 FPGA, U46
  5. eMMC RAM, U1
  6. Dual QSPI Flash, U32, U33
  7. Crypto Authentication IC, U19
  8. OPTIGA Trust M Authentication IC, U16
  9. EEPROM MAC Address, U14
  10. USB2.0 Transceiver, U2
  11. Gigabit Ethernet Transceiver, U17
  12. B2B Connector, J2
  13. B2B Connector, J3
  14. B2B Connector, J1
  15. B2B Connector, J4
  16. Power Terminal, J5
  17. Configurable Regulator, U20

Initial Delivery State

Storage device name

Content

Notes

Quad SPI Flash

Not Programmed


EEPROMProgrammed

MAC Address

System Controller CPLDProgrammedIntel MAX 10
PL DDR4 SDRAMNot Programmed
PS DDR4 SDRAMNot Programmed
eMMCNot Programmed
Initial delivery state of programmable devices on the module

Configuration Signals

Function

SchematicConnected toDirectionDescription

Boot Mode

MODE0...3B2B, J3AInput
ResetPERST0B2B, J1BInput
Power GoodPG_SOMB2B, J2BOutput
Power EnableEN_SOMB2B, J2BInput
Manual ResetMR

B2B, J2B

CPLD, U46

Output

Output


Power SignalPG_+3.3VB2B, J2BOutput
Battery SupplyV_BATBank PSCONFIGInput
Control SignalDONEB2B, J3BOutputPull up
Control SignalPOR_BB2B, J3BInputPull up
Initialization SignalINIT_BB2B, J3BOutputPull up
Program SignalPROG_BB2B, J3BOutputPull up
Reset SignalSRST_BB2B, J3BInputPull up
Controller signal.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

BankType

B2B Connector

I/O Signal Count

VoltageNotes

67

IO HP

J1

48x SE / 24x DIFF

Variable

Maximum 1.8 V

66

IO HP

J1

48x SE / 24x DIFF

Variable

Maximum 1.8 V

64

IO HP

J1

48x SE / 24x DIFF

Variable

Maximum 1.8 V

65

IO HP

J1

49x SE / 24x DIFF

Variable

Maximum 1.8 V

91

IO HD

J2

24x SE / 12x DIFF

Variable

Maximum 3.3 V

90

IO HD

J2

24x SE / 12x DIFF

Variable

Maximum 3.3 V

89

IO HD

J2

24x SE / 12x DIFF

Variable

Maximum 3.3 V

68

IO HP

J2

51x SE / 24x DIFF

Variable

Maximum 1.8 V

88

IO HD

J2

4x SE /  2x DIFF

Variable

Maximum 3.3 V

70

IO HP

J2

12x SE / 6x DIFF

1.20 V


128 to 131

GTY

J3

16x MGT (RX/TX)

0.90 V


128 to 131

GTY CLK

J3

4x MGT CLK

0.90 V


505

GTR

J3

4x MGT (RX/TX)

0.85 V


505

GTR CLK

J3

2x MGT CLK

0.85 V


-

USB Data

J3

1x DIFF

-


-

ETH MDIO

J3

4x DIFF

-


501IO MIO

J2

25x SE

Variable

Maximum 3.3 V

500

IO MIO

J3

2x SE

1.80 V

88

IO HD

J4

20x SE / 10x DIFF

Variable

Maximum 3.3 V

224 to 231

GTR

J4

32x MGT (RX/TX)

0.90 V


224 to 231

GTR CLK

J4

8x DIFF

0.90 V


General PL I/O to B2B connectors information

For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq UltraScale+ device used on the TE0865 module has 4x Lanes MGT transceivers connected to Bank 505 PSGTR. All 4x lanes are wired directly to B2B connector J3B consisting of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Furthuremore, MGT clocks are sourced by oscillators U3 and U4 at 27 and 100 MHz respectively.
Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

BankPinSignal NameB2B PinNote
505
(PSGTR)



MGT Lane  0 
  • GTR_RX0_P
  • GTR_RX0_N
  • GTR_TX0_P
  • GTR_TX0_N
  • J3B-D39
  • J3B-D40
  • J3B-C38
  • J3B-C39

MGT Lane 1
  • GTR_RX1_P
  • GTR_RX1_N
  • GTR_TX1_P
  • GTR_TX1_N
  • J3B-D36
  • J3B-D37
  • J3B-C35
  • J3B-C36

MGT Lane 2
  • GTR_RX2_P
  • GTR_RX2_N
  • GTR_TX2_P
  • GTR_TX2_N
  • J3B-D33
  • J3B-D34
  • J3B-C32
  • J3B-C33

MGT Lane 3
  • GTR_RX3_P
  • GTR_RX3_N
  • GTR_TX3_P
  • GTR_TX3_N
  • J3B-D30
  • J3B-D31
  • J3B-C29
  • J3B-C30

MGT_CLK0MGT505_CLK0 (P/N)Oscillator, U327 MHz
MGT_CLK1MGT505_CLK1 (P/N)Oscillator, U4100 MHz
MGT_CLK2
  • MGT505_CLK2_P
  • MGT505_CLK2_N
  • J3A-A29
  • J3A-A30

MGT_CLK3
  • MGT505_CLK2_P
  • MGT505_CLK2_N
  • J3A-B30
  • J3A-B31

MGT Lanes connection

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.JTAG Interface

JTAG access to the UltraScale+ MPsoC FPGA through B2B connector J3B.

JTAG Signal

B2B Connector

TMSJ3B- D59
TDIJ3B- D57
TDOJ3B- D58
TCK

J3B- D56

JTAG pins connection

JTAG access to the system controller CPLD, Intel MAX10 FPGA(U46) through B2B connector J2B.

JTAG Signal

B2B Connector

TCK_MAX10J2B- D56
TMS_MAX10J2B- D57
TDO_MAX10J2B- D58
TDI_MAX10

J2B- D59

JTAGENPulled Up
JTAG pins connection

I2C Addresses

I2C AddressDesignatorNotes
0x53U14EEPROM
0x30U16OPTIGA Trust M
0x4EU20Configurable Regulator
I2C addresses

MIO Pins

MIO PinConnected toNotes
MIO0...5QSPI Flash, U32
MIO6...11QSPI, Flash, U33
MIO13...22eMMC, U1
MIO23B2B, J2AU_INIT
MIO24...25B2B, J3BI2C  via Voltage Transform, U15
MIO26...27B2B, J2AUART0_RX
MIO28...29B2B, J2AUART1_RX
MIO30...31B2B, J2AI2C via Voltage Transform, U12
MIO32...37B2B, J2AGPIO0...5
MIO38B2B, J2AM_INIT
MIO39...42B2B, J2BSD
MIO43B2B, J2APS_RSTn
MIO44...51B2B, J2ASD
MIO52...63USB2.0, U2USB2.0
MIO64...77ETH PHY, U17ETH PHY
MIOs pins

Test Points

Test PointSignalNotes
TP1...2+12.0V
TP3...4+3.3V
TP5...6+3.3V_SW
TP7...8+2.3V
TP9...10+1.8V
TP11...12+1.8V_AUX
TP13...14+1.8V_VCCADC
TP15...16+0.85V_VCCINT
TP17...18+1.2V_PL_DDR
TP19...20+2.5V_PL_DDR
TP21...22+0.85V_GTR_AVCC_PS
TP23...24+1.8V_GTR_AVTT_PS
TP25...26+1.8V_AUX_PS
TP27...28+1.2V_PLL_PS
TP29...30+1.2V_PS_DDR
TP31...32+2.5V_PS_DDR
TP33...34VREFA_DDR_PS
TP35...36VREFA_DDR_PL
TP37...38VTT_DDR_PS
TP39...40VTT_DDR_PL
TP41...42+0.9V_GTH_AVCC
TP43...44+1.8V_GTH_AUX
TP45...46+1.2V_GTH_AVTT
TP47...48+0.9V_GTY_AVCC
TP49...50+1.8V_GTY_AUX
TP51...52+1.2V_GTY_AVTT
Test Points Information

On-board Peripherals

On board peripherals

System Controller CPLD

The TE0865 is equipped with an Intel MAX 10 as System Controller CPLD (U46). Please check further information in the TE0865 CPLD page.

BankSchematicConnectced toNotes
Bank 1AVCCIO1A3.3V
Bank 1BTCK_MAX10B2B, J2B
TMS_MAX10B2B, J2B
TDO_MAX10B2B, J2B
TDI_MAX10B2B, J2B
VCCIO1B3.3V
Bank 2EN_VTT_DDR_PLRegulator, U26
EN_+2.5V_PL_DDRRegulator, U22Enable Power DDR4 PL
EN_+1.2V_PL_DDRRegulator, U24Enable Power DDR4 PL
PG_+1.2V_PL_DDRRegulator, U24Power Good DDR4 PL
EN_+1.8V_AUX_PSRegulator, U43
EN_SOMB2B, J2BMain 'Power Enable' signal
PG_SOMB2B, J2BMain 'Power Good' signal
SC_EXT_2...3B2B, J2B
PG_VCCINTRegulator, U20Configurable Regulator
LTM_FAULTRegulator, U20Configurable Regulator
MR

B2B, J2B

Regulator, U51


Bank 3SMB_ALERTnRegulator, U20Configurable Regulator
PG_+2.5V_PL_DDRRegulator, U22Power Good DDR4 PL
LTM_RUNP_ENRegulator, U20Configurable Regulator
M_SDAI2C  BusB2B, J2A via level shifter (U12)
M_SCLI2C  BusB2B, J2A via level shifter (U12)
RST_SYSnDiod, U53BReset
EN_+0.9V_GTH_AVCCRegulator, U35
EN_+0.9V_GTY_AVCCRegulator, U38
PG_+1.2V_PS_DDRRegulator, U25Power Good DDR4 PS
PG_+0.9V_GTH_AVCCRegulator, U35
PG_+0.9V_GTY_AVCCRegulator, U38
EN_+3.3V_SWRegulator, U52Secondary Power
EN_+1.2V_PLL_PSRegulator, U42
PG_+1.8V_GTR_AVTT_PSRegulator, U47
PG_+1.8VRegulator, U41
EN_+2.5V_PS_DDRRegulator, U23Enable Power DDR4 PS
PG_+1.2V_GTY_AVTTRegulator, U39
EN_+1.2V_GTY_AVTTRegulator, U39
M_INTB2B, J2A
EN_+1.8V_VCCADCRegulator, U49
PG_+0.85V_GTR_AVCC_PSRegulator, U48
EN_VTT_DDR_PSRegulator, U27
EN_+1.8VRegulator, U41
EN_+1.8V_GTY_AUXRegulator, U40
PG_+2.3VRegulator, U45
Bank 6VCCIO63.3V
Bank 5EN_+1.8V_GTR_AVTT_PSRegulator, U47
EN_+1.8V_GTH_AUXRegulator, U37
EN_+1.8V_AUXRegulator, U50
EN_+1.2V_GTH_AVTTRegulator, 36
PG_+1.2V_GTH_AVTTregulator, U36
+3.3V_SWeMMC, U1
EN_+1.2V_PS_DDRRegulator, U25Power Good DDR4 PS
EN_+0.85V_GTR_AVCC_PSRegulator, U48
PG_+1.2V_GTH_AVTTRegulator, U48
EN_VCCINTRegulator, U20
EN_+2.3VRegulator, U45
PG_+1.8V_AUXRegulator, U50
PG_+2.5V_PS_DDRRegulator, U23Power Good DDR4 PS
CPLD pin connections

Dual QSPI Flash Memory

The TE0865 is equipped with dual 128 Mb (256 Mb) QSPI flash memory, U32 and U33 for configuration and operation storage.

DesignatorPinSchematicNotes
U32CLKMIO0
DI/IO0 MIO4
DO/IO1MIO1
nWP/IO2MIO2
nHOLD/IO3MIO3
nCSMIO5
U33CLKMIO12
DI/IO0 MIO8
DO/IO1MIO9
nWP/IO2MIO10
nHOLD/IO3MIO11
nCSMIO7
Quad SPI interface MIOs and pins

eMMC Memory

The TE0865 is equipped with an eMMC Flash memory IC(U1) connected to the PS MIO pins MIO13..MIO22. 

DesignatorPinSchematicConnected to Notes
U32CLKMMC-CCLKMIO22
nRESETRST_PERn-PS_RSTn, PS_SYSn
CMDMMC-CMDMIO21
DAT0...7MMCD0...7MIO13...20
eMMC connections

Gigabit Ethernet

On-board Gigabit Ethernet PHY (U17) is provided with Marvell Alaska 88E1512 IC (U17). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the ETH is supplied from an on-board 25.00 MHz oscillator (U18).

PinSchematicConnected toNote
MDIP0...3

PHY_MDI0...3

B2B, J3A


MDC

ETH_MDC

MIO76


MDIOETH_MDIOMIO77
S_INS_INN.C
S_OUTS_OUTN.C
TXD0..3ETH_TXD0...3MIO65...68
TX_CTRLETH_TXCTLMIO69
TX_CLKETH_TXCKMIO64
RXD0...3ETH_RXD0...3MIO71...74
RX_CTRLETH_RXCTLMIO75
RX_CLKETH_RXCKMIO70
LED1PHY_LED1B2B, J3A
RESETnETH_RSTMIO24
XTAL_INETH_CLKOscillator, U18Input Clock of ETH Transciever
nRESETRST_PERnB2B, J2APS_RSTn, PS_SYSn
GigaBit Ethernet connection

USB2.0 Transceiver

Hi-speed USB2.0 transceiver (U2) is provided with USB3340 from Microchip. The transceiver is connected to the PS MIO via MIO52..63. The I/O voltage is fixed at 3.3V (VBAT) and PHY reference clock input is supplied from the on-board 24.00 MHz oscillator (U13).

 PinSchematicMIOB2B NameNotes
RESETBRST_PERn-
RST_PERn
VBATVBAT-
3.3V
CPENUSB_CPEN-B2B, J3A
VBUSUSB_VBUS-B2B, J3A
IDUSB_ID-B2B, J3A
DP, DM

USB_DP

USB_ DM

-B2B, J3A
REFCLKUSB_CLK24_PHY--24.00MHz from on-board oscillator (U13).
REFSEL[0..2]---Reference clock frequency select, all set to 1.8V selects 24 MHz.
DATA0...7USB_DATA0...7

MIO 56,57,54, 59...62

-USB Data
STPUSB_STPMIO58-
NXTUSB_NXTMIO55-
DIUSB_DIMIO53-
CLKOUTUSB_CLKOUTMIO52-
General overview of the USB PHY signals

EEPROM

There is an EEPROM (U14) provided on the module TE0865 for storing MAC Address. The EEPROM has the I2C bus address 0x53.

MIO PinSchematicU25 PinNotes
MIO39I2C_SDASDA
MIO38I2C_SCLSCL
I2C EEPROM interface MIOs and pins

Crypto Authentication

The TE0865 is equipped with an authentication IC, ATECC608A (U19) which includes an EEPROM array for storage of up to 16 keys, certificates, miscellaneous read/write, read-only or secret data, consumption logging, and security configurations. Access to the various sections of memory can be restricted in a variety of ways and then the configuration can be locked to prevent changes.

PinSchematicConnected toNotes
SDAM_SDAB2B, J2AM_SDA_PS
SCLM_SDAB2B, J2AM_SCL_PS
Crypto Authentication connection

OPTIGA Authentication

The TE0865 is equipped with an OPTIGA Trust M  IC, SLS32AIA010MH (U16). The OPTIGA Trust M comes with up to 10kB of user memory that can be used to store X.509 certificates and data. OPTIGA Trust M is based on Common Criteria (CC) Certified EAL6+ (high) hardware enabling it to prevent physical attacks on the device itself and providing high assurance that the keys or arbitrary data stored cannot be accessed by an unauthorized entity. The OPTIGA Trust M is connected via I2C with address of 0x30.

PinSchematicConnected toNotes
SDAM_SDAB2B, J2A
SCLM_SDAB2B, J2A
RSTRST_SECnB2B, J2APS_RSTn
OPTIGA Authentication connection

PL DDR4 SDRAM

The TE0865 SoM has four volatile DDR4 SDRAM ICs connected to Programmable Logic(PL) for operations, storing and streaming data.

  • Part number:  MT40A1G16RC-062E*
  • Supply voltage: 1.2V
  • Speed: 3200 MT/s*
  • Temperature: -40 ~ 95 °C*

* depends on assembly version

PS DDR4 SDRAM

The TE0865 SoM has five volatile DDR4 SDRAM ICs connected to Processing System (PS) for operations, storing and streaming data.

  • Part number:  MT40A1G16RC-062E*
  • Supply voltage: 1.2V
  • Speed: 3200 MT/s*
  • Temperature: -40 ~ 95 °C*

* depends on assembly version

Clock Sources

DesignatorDescriptionFrequencyNote
U3MEMS Oscillator27 MHzMGT_CLK0
U4MEMS Oscillator100 MHzMGT_CLK1
U13MEMS Oscillator24 MHzUSB_CLK
U18MEMS Oscillator25 MHzETH_CLK
U31MEMS Oscillator200 MHzDDR4 Clock
U34MEMS Oscillator33.33 MHzPS REF CLK
Osillators

Power and Power-On Sequence

Power Supply

Power supply 12V +/- 5% with minimum current capability of 3.0 A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
+12.0VTBD*
Power Consumption

* TBD - To Be Determined

Power Distribution Dependencies

Power Distribution

Power-On Sequence

Power Sequency

Voltage Monitor Circuit

The LTM4700 (U20) is a dual 50A or single 100A step-down µModule(power module) DC/DC regulator featuring remote configurability and telemetry-monitoring of power management parameters over standard I2C-based digital interface protocol.

Voltage Monitor Circuit

Power Rails

Power Rail Name

B2B J1 Pin

B2B J2 Pin

B2B J3 Pin

B2B J4 PinDirectionNotes
VCCIO_67D10---In
VCCIO_66D20---In
VCCIO_64D35---In

VCCIO_65

D45---In
VCCIO_91-A6,--In
VCCIO_90-B10--In
VCCIO_89-A21--In
V_IO_CFG-A45--In
+1.2V_PL_DDR-B44--Out
VCCIO_68-C29--In
VCCIO_88-D44--In
+3.3V-D60--Out
+1.8V-
D60-Out
Module power rails.

Bank Voltages

Bank          

Schematic Name

Voltage

Notes
64 HPVCCIO_64max 1.8 V
65 HP VCCIO_65max 1.8 V
66 HPVCCIO_66max 1.8 V
67 HP VCCIO_67max 1.8 V
68 HPVCCIO_68max 1.8 V
69 HP VCCIO_691.2 V


70 HPVCCIO_701.2 V


71 HPVCCIO_711.2 V
88 HDVCCIO_88max 3.3VZU17 Bank 90 HD
89 HDVCCIO_88max 3.3 VZU17 Bank 91 HD
90 HDVCCIO_88max 3.3VZU17 Bank 93 HD
91 HDVCCIO_88max 3.3VZU17 Bank 94 HD
128 GTYMGTAVCC_L0.9 V
129 GTYMGTAVCC_L0.9 V
224 GTHMGTAVCC_RS0.9 V
225 GTHMGTAVCC_RS0.9 V
228 GTHMGTAVCC_RN0.9 V
229 GTHMGTAVCC_RN0.9 V
500 PSMIOVCCO_PSIO0_5001.8 V
501 PSMIOVCCO_PSIO0_501max 3.3 V
502 PSMIOVCCO_PSIO0_5021.8 V
504 PSDDRVCCO_PSDDR_5041.2 V
505 PSGTRPS_MGTRAVCC0.85 V
Zynq SoC bank voltages.


Board to Board Connectors

The 7.5 x 10 modules use four Samtec AcceleRate HD High-Density on the bottom side.
  • 4x ADM6-60-01.5-L-4-2 (legacy) or ADM6-60-01.5-L-4-0 (240 pins, 60 per row)
    •  Mates with ADF6-60-03.5-L-4-2 (legacy) or ADF6-60-03.5-L-4-0

The carriers for 7.5 x 10 modules use four Samtec AcceleRate HD High-Density on the bottom side.

  • 4x ADF6-60-03.5-L-4-2 (legacy) or ADF6-60-03.5-L-4-0 (240 pins, 60 per row)
    • Mates with ADM6-60-01.5-L-4-0 (legacy) or ADM6-60-01.5-L-4-2
Features
  • Board-to-Board connector 240-pins, 60 contacts per row
  • Pitch:           0.025" (0.635 mm)
  • Data Rate:
    • ADM6-XX-XX.X-X-X-2: 56 Gbps
    • ADM6-XX-XX.X-X-X-0: 64 Gbps
  • Mates with: ADM6/APF6
  • Insulator Material: Black LCP
  • Contact Material:  Copper Alloy
  • Plating:                 Au or Sn over 50 µ" (1.27 µm) N
  • Operating Temperature Range: -55 ºC to +125 ºC
  • Lead-Free solderable: Yes
  • RoHS Compliant:        Yes
Connector Mating height

When using the same type on baseboard, the mating height is 5 mm. Other mating heights are possible by using connectors with a different height:

Order numberREF numberSamtec NumberTypeContribution to stacking heightComment
30095REF-30095ADM6-60-01.5-L-4-2Module connector1.5 mmStandard connector used on modules (legacy)
- -ADM6-60-01.5-L-4-0Module connector1.5 mmAlternative connector
31137REF-31137ADF6-60-03.5-L-4-2Baseboard connector3.5 mmStandard connector used on carrier (legacy)
--ADF6-60-03.5-L-4-0Baseboard connector3.5 mmAlternative connector
Connectors.

The module can be manufactured using other connectors upon request.

Connector Speed Ratings

The AcceleRate HD High-Density connector speed rating depends on the stacking height; please see the following table:

ConnectorStacking heightSpeed rating
ADM6-XX-XX.X-X-X-25 mm56 Gbps
ADM6-XX-XX.X-X-X-05 mm64 Gbps
Speed rating.
Current Rating

Current rating of Samtec AcceleRate HD High-Density B2B connectors is 1.34 A per pin (4 pins powered).

Connector Mechanical Ratings
  • Shock:      100G, 6 ms Sine
  • Vibration:  7.5G random, 2 hours per axis, 3 axes total




Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnitNote
+12.0VInput Supply Voltage5.7516VB2B, J5
V_IO_CFGBank 501 Voltage-0.53.4VB2B, J3
VCCIO_64Bank 64 Supply Voltage-0.52VB2B, J1
VCCIO_65Bank 65 Supply Voltage-0.52VB2B, J1
VCCIO_66Bank 66 Supply Voltage-0.52VB2B, J1
VCCIO_67Bank 67 Supply Voltage-0.52VB2B, J1
VCCIO_68Bank 68 Supply Voltage-0.52VB2B, J2
VCCIO_88Bank 88 Supply Voltage-0.53.4VB2B, J2
VCCIO_89Bank 89 Supply Voltage-0.53.4VB2B, J2
VCCIO_90Bank 90 Supply Voltage-0.53.4VB2B, J2
VCCIO_91Bank 91 Supply Voltage-0.53.4VB2B, J2
T_STGStorage Temperature-4085°C
PS absolute maximum ratings

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

  • Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
  • Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
  • Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

  • Customer SoC design. The allowed main SoC temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
  • Cooling solution, active and or passive cooling.
  • Climate or environmental conditions besides ambient temperature range.
  • Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.

Classification of the module can be locked up here: Article Number Information i.e.: TE0865-02-DG'I'83MA, the 'I' indicates that all components are at least in Industrial temperature class).

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

ParameterMinMaxUnitsReference Document
+12.0V11.412.6VSee  LTM4700 (U20) datasheet.
V_IO_CFG1.143.4V
VCCIO_640.951.9V
VCCIO_650.951.9V
VCCIO_660.951.9V
VCCIO_670.951.9V
VCCIO_680.951.9V
VCCIO_881.143.4V
VCCIO_891.143.4V
VCCIO_901.143.4V
VCCIO_911.143.4V
Recommended operating conditions.


Physical Dimensions

  • Module size: 75 mm × 100 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

PCB thickness: 2 mm.

Physical Dimension

Currently Offered Variants 

Trenz shop TE0865 overview page
English pageGerman page
Trenz Electronic Shop Overview

Revision History

Hardware Revision History

Board hardware revision number.


DateRevisionChangesDocumentation Link
2021-04-15REV01Initial ReleaseREV01
2021-10-21REV02
  • Improved PCB trace to simplify production with increased reliability
  • All pull down resistors on DCDC enable inputs changed to 1K
REV02
Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

DateRevisionContributorDescription

v.87


  • Updated IO listings in Key Features and Board to Board I/Os

2025-08-27

v.86


Martin Rohrmüller

  • Reworked recommended temperature range according to template 4.3

2025-03-14

v.78

Antti Lukats

  • Power: VCCR is renamed to +12.0V
  • Power: Added absolute and recommended voltage range for HD banks.
  • Added +12.0V voltage tolerance.
  • VIN renamed to +12.0V
  • Changed V_IO_CFG voltage description
  • Key features: added MGT information

2024-03-06

v.74


Vadim Yunitski


  • Key features: default DDR4 capacity changed to 4GB
  • Added a notes in PL DDR4 SDRAM and PL DDR4 SDRAM chapter

  • Minor change in Overview chapter
2024-02-07

V.71

John Hartfiel 

  • Correction Maximum DDR Speed on Key features according AMD Datasheet (still depends assembled ZynqMP)


2023-10-24


v.69

John Hartfiel 

  • Correction Overview Picture GTH B2B connection

2023-07-05


v.68

Vadim Yunitski

  • Updated table "CPLD Pin Connections": added signals EN_SOM and PG_SOM; SC_EXT_1 and SC_EXT_4 removed.
  • Updated table "Controller signals": PG_VCCINT and EN_VCCINT replaced by PG_SOM and EN_SOM. Description updated respectivelly
  • Block diagram updated: added PG_SOM and EN_SOM; SC_EXT_1 and SC_EXT_4 removed.
2022-10-17


v.67


JH


  • Update link to the download area

2022-05-30v.66ED
  • Update to the latest version

--

all

  • --
Document change history.

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Product Disclaimer

Products (incl. Software and Firmware) are exclusively designed, manufactured, and distributed for industrial applications. They are not intended, authorized, or certified for use in critical safety applications, medical devices, aerospace, nuclear, life-support, traffic-control, military, or other environments where malfunction or failure could result in personal injury, death, or significant property or environmental damage.

Trenz Electronic GmbH (“Manufacturer”) excludes any liability for inappropriate use in such contexts. The Customer bears all responsibility for verifying suitability and compliance with applicable regulations when deploying in any critical-use scenario. The Customer also agrees to indemnify and hold harmless the Manufacturer from any third-party claims or liabilities arising from such use.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.



Table of contents