TE0714 Test Board

Overview

This example contains a simple MicroBlaze Design with an endless loop application printing "Hello Trenz Module TE0714" and letting the onBoard LED blink.

Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.

Key Features

• Vitis/Vivado 2021.2
• MicroBlaze
• UART
• QSPI Flash
• Fmeter

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0714 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   _create_win_setup.cmd/_create_linux_setup.sh

   ------------------------Set design paths----------------------------
   -- Run Design with: _create_win_setup
   -- Use Design Path: <absolute project path>
   --------------------------------------------------------------------
   -------------------------TE Reference Design---------------------------
   --------------------------------------------------------------------
   -- (0)  Module selection guide, project creation...prebuilt export...
   -- (1)  Create minimum setup of CMD-Files and exit Batch
   -- (2)  Create maximum setup of CMD-Files and exit Batch
   -- (3)  (internal only) Dev
   -- (4)  (internal only) Prod
   -- (c)  Go to CMD-File Generation (Manual setup)
   -- (d)  Go to Documentation (Web Documentation)
   -- (g)  Install Board Files from Xilinx Board Store (beta)
   -- (a)  Start design with unsupported Vivado Version (beta)
   -- (x)  Exit Batch (nothing is done!)
   ----
   Select (ex.:'0' for module selection guide):

2. Press 0 and enter to start "Module Selection Guide"
3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
   

   • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note: Select correct one, see also Vivado Board Part Flow

4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

   run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")

   TE::hw_build_design -export_prebuilt

   Using Vivado GUI is the same, except file export to prebuilt folder.

5. Generate Programming Files with Vitis

   1. Run on Vivado TCL:

      Script generates applications and bootable files, which are defined in "sw_lib\apps_list.csv"

      TE::sw_run_vitis -all

   2. The newly built application "\prebuilt\software\<short name>\hello_te0714.elf" gets copied into  "\firmware\microblaze_0\"

   3. Regenerate Vivado Project or Update Bitfile only, with new "hello_te0714.elf"

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   run on Vivado TCL (Script programs BOOT.bin on QSPI flash)

   TE::pr_program_flash -swapp hello_te0714

3. Power your Board OFF and ON to start the application and see the output in the console

JTAG

Not used on this example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)

3. Select QSPI as Boot Mode

   Note: See TRM of the Carrier, which is used.

4. Power On PCB

   boot process

   1. FPGA Loads Bitfile from Flash

   2. hello_te0714.elf application starts on MicroBlaze

   3. Hello Trenz will be printed on UART console

     info: Do not reboot, if Bitfile programming over JTAG is used as programming method.

   1. UART

      Open Serial Console (e.g. putty)

      1. Speed: 9600
      2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
         

Vivado HW Manager

• Open Vivado HW Manager
• Add VIO to Dashboard
• Set Radix to unsigned integer for FMeterCLKs (fm_*). Note: Measurement is not accurate!
  
• Control:
  
  1. system Reset
     
  2. Enable MGT Power & Clock

System Design - Vivado

Block Design

Block Design

Constraints

Basic module constraints

#
# Default common settings that do not depend assembly variant
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

#check mgt clock routing
set_false_path -from [get_clocks mgt_clock1_clk_p] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_1/inst/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[1].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[43]/D}]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[1].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[40]/D}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_1/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks mgt_clock1_clk_p]
set_multicycle_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[1].COUNTER_F_inst/bl.DSP48E_2/RSTINMODE}] 1

For 1.8V variants:

set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

For 3.3V variants:

set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Design specific constraints

All others IOs are constraint in the Board Files.

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

Template location: "<project folder>\sw_lib\sw_apps\"

Hello TE0714

Trenz Hello World example and frequency read as endless loop

Template location: \sw_lib\sw_apps\hello_te0714

The printed Text and the blinking of the red LED can be modified

Additional Software

No additional software is needed.

App. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

Legal Notices