- Created by Waldemar Hanemann, last modified on 24 03, 2023
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Overview
Refer to http://trenz.org/te0763-info for the current online version of this manual and other available documentation.
Key Features
- Vitis/Vivado 2021.2
- MicroBlaze
- I2C
- QSPI Flash
- FMeter
- MIG
Revision History
Date | Vivado | Project Built | Authors | Description |
---|---|---|---|---|
2023-03-24 | 2021.2 | TE0763-test_board_noprebuilt-vivado_2021.2-build_20_20230324094232.zip | Waldemar Hanemann |
|
Release Notes and Know Issues
Issues | Description | Workaround | To be fixed version |
---|---|---|---|
No known issues | --- | --- | --- |
Requirements
Software
Software | Version | Note |
---|---|---|
Vitis | 2021.2 | needed, Vivado is included into Vitis installation |
PetaLinux | 2021.2 | needed |
Hardware
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|---|---|---|---|---|---|---|
TE0763-01-82I51-A* | 200_2i_128mb | REV01 | 128MB | 32MB | NA | NA | NA |
*used as reference
Design supports following carriers:
Carrier Model | Notes |
---|---|
TE0303* |
*used as reference
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
Power supply for Carrier | Voltage depends on carrier (5V for TE0303) |
Xilinx Platform Cable USB 2 with Typ B USB cable | For Programming and Debugging |
*used as reference
Content
For general structure and usage of the reference design, see Project Delivery - Xilinx devices
Design Sources
Type | Location | Notes |
---|---|---|
Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts |
Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
Additional Sources
Type | Location | Notes |
---|---|---|
Prebuilt
File | File-Extension | Description |
---|---|---|
BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Boot Script-File | *.scr | Distro Boot Script file |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Debian SD-Image | *.img | Debian Image for SD-Card |
Diverse Reports | --- | Report files in different formats |
Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) |
Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/Vitis version. Do never use different Versions of Xilinx Software for the same project.
Reference Design for download is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- Xilinx Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
_create_win_setup.cmd/_create_linux_setup.sh------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow
Create Bitstream and hardware description file (.xsa file) and export to prebuilt folder
run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")TE::hw_build_design -export_prebuilt
Using Vivado GUI to generate the Bitstream is the same, except file export to prebuilt folder.
Generate Programming Files with Vitis
run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Launch
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for hello_te0763.mcs on QSPI Flash.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
run on Vivado TCL (Script programs BOOT.bin on QSPI flash)TE::pr_program_flash -swapp hello_te0763
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
- Set Boot Mode to QSPI-Boot.
- Depends on Carrier, see carrier TRM.
JTAG
- Connect JTAG and power on PCB
- Open Vivado HW Manager
- Program FPGA with Bitfile from "prebuilt\hardware\<short dir>\"
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select QSPI Boot Mode
Note: See TRM of the Carrier, which is used.
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scrJTAG Console:
- Connect the Platform Cable and Launch XSCT or the XSDB console:
- type: connect
- type: targets -set -filter {name =~ "MicroBlaze Debug*"} -index 0
- type: jtagterminal -start
- Terminal starts printing out "Hello Trenz Module" in a loop:
1. FPGA loads Bitstream(hello_te0763 application included) from Flash
2. The hello_te0763.elf application starts
2. Hello Trenz will be run on JTAG console
- Connect the Platform Cable and Launch XSCT or the XSDB console:
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Set radix from VIO signals (clk_2, clk_0, fpga_24MHz, SYSCLK_100MHz) to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz - Monitoring: Four Clocks, status and various reset signals and
System Design - Vivado
Block Design
Constraints
Basic module constraints
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] # # #
Design specific constraints
#CLKS set_property PACKAGE_PIN Y18 [get_ports {FPGA_24MHz[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_24MHz[0]}] set_property PACKAGE_PIN C18 [get_ports {SYSCLK[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {SYSCLK[0]}]
## Clock signal create_clock -period 41.666 -name {CLK1B[0]} -waveform {0.000 20.833} [get_ports {FPGA_24MHz[0]}] create_clock -period 10.000 -name {CLK1B[0]} -waveform {0.000 5.000} [get_ports {SYSCLK[0]}]
Software Design - Vitis
For Vitis project creation, follow instructions from:
Application
Template location: "<project folder>\sw_lib\sw_apps\"
Hello TE0763
Trenz Hello World example as endless loop instead of one console output.
Template location: \sw_lib\sw_apps\hello_te0717
Additional Software
Cypress USB Controller
Software and Firmware modified to work with TE0763
Link to TE-USB-Suite-Master
App. A: Change History and Legal Notices
Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
Date | Document Revision | Authors | Description |
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Legal Notices
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
Limitation of Liability
In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.
Copyright Notice
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
Environmental Protection
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH, RoHS and WEEE
REACH
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
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