TE0763 Test Board

Overview

Refer to http://trenz.org/te0763-info for the current online version of this manual and other available documentation.

Key Features

• Vitis/Vivado 2021.2
• MicroBlaze
• I2C
• QSPI Flash
• FMeter
• MIG

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis version. Do never use different Versions of Xilinx Software for the same project.

Reference Design for download is available on:

• TE0763 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides

• Vivado Projects - TE Reference Design

• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   _create_win_setup.cmd/_create_linux_setup.sh

   ------------------------Set design paths----------------------------
   -- Run Design with: _create_win_setup
   -- Use Design Path: <absolute project path>
   --------------------------------------------------------------------
   -------------------------TE Reference Design---------------------------
   --------------------------------------------------------------------
   -- (0)  Module selection guide, project creation...prebuilt export...
   -- (1)  Create minimum setup of CMD-Files and exit Batch
   -- (2)  Create maximum setup of CMD-Files and exit Batch
   -- (3)  (internal only) Dev
   -- (4)  (internal only) Prod
   -- (c)  Go to CMD-File Generation (Manual setup)
   -- (d)  Go to Documentation (Web Documentation)
   -- (g)  Install Board Files from Xilinx Board Store (beta)
   -- (a)  Start design with unsupported Vivado Version (beta)
   -- (x)  Exit Batch (nothing is done!)
   ----
   Select (ex.:'0' for module selection guide):

2. Press 0 and enter to start "Module Selection Guide"
3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
   

   • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note: Select correct one, see also Vivado Board Part Flow

4. Create Bitstream and hardware description file (.xsa file) and export to prebuilt folder

   run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")

   TE::hw_build_design -export_prebuilt

   Using Vivado GUI to generate the Bitstream is the same, except file export to prebuilt folder.

5. Generate Programming Files with Vitis

   run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")

   TE::sw_run_vitis -all
   TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

   TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for hello_te0763.mcs on QSPI Flash.

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   run on Vivado TCL (Script programs BOOT.bin on QSPI flash)

   TE::pr_program_flash -swapp hello_te0763

   To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

3. Set Boot Mode to QSPI-Boot.
   • Depends on Carrier, see carrier TRM.

JTAG

1. Connect JTAG and power on PCB
2. Open Vivado HW Manager
3. Program FPGA with Bitfile from "prebuilt\hardware\<short dir>\"

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)

3. Select QSPI Boot Mode

   Note: See TRM of the Carrier, which is used.

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
   The boot options described above describe the common boot processes for this hardware; other boot options are possible.
   For more information see Distro Boot with Boot.scr

4. JTAG Console:

   • Connect the Platform Cable and Launch XSCT or the XSDB console:
     • type: connect
     • type: targets -set -filter {name =~ "MicroBlaze Debug*"} -index 0
     • type: jtagterminal -start
     • Terminal starts printing out "Hello Trenz Module" in a loop:
       boot process

       1. FPGA loads Bitstream(hello_te0763 application included) from Flash

       2. The hello_te0763.elf application starts

       2. Hello Trenz will be run on JTAG console
       
       

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• Set radix from VIO signals (clk_2, clk_0, fpga_24MHz, SYSCLK_100MHz) to unsigned integer.
  Note: Frequency Counter is inaccurate and displayed unit is Hz
  
• Monitoring: Four Clocks, status and various reset signals and
  

Vivado Hardware Manager

System Design - Vivado

Block Design

Constraints

Basic module constraints

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx1 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
#
#
#

Design specific constraints

#CLKS
set_property PACKAGE_PIN Y18 [get_ports {FPGA_24MHz[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_24MHz[0]}]

set_property PACKAGE_PIN C18 [get_ports {SYSCLK[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SYSCLK[0]}]

## Clock signal
create_clock -period 41.666 -name {CLK1B[0]} -waveform {0.000 20.833} [get_ports {FPGA_24MHz[0]}]
create_clock -period 10.000 -name {CLK1B[0]} -waveform {0.000 5.000} [get_ports {SYSCLK[0]}]

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

Template location: "<project folder>\sw_lib\sw_apps\"

Hello TE0763

Trenz Hello World example as endless loop instead of one console output.

Template location: \sw_lib\sw_apps\hello_te0763

Additional Software

Cypress USB Controller

Software and Firmware modified to work with TE0763

Link to TE-USB-Suite-Master

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