- Created by John Hartfiel, last modified by Manuela Strücker on 28 09, 2022
You are viewing an old version of this page. View the current version.
Compare with Current View Page History
« Previous Version 74 Next »
Overview
ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0820-info
Key Features
- Vitis/Vivado 2021.2.1
- PetaLinux
- SD
- ETH
- USB
- I2C
- RTC
- FMeter
- MAC from EEPROM
- User LED (PCB REV03 only)
- Modified FSBL for SI5338 programming
- Special FSBL for QSPI programming
Revision History
Date | Vivado | Project Built | Authors | Description |
---|---|---|---|---|
2022-09-28 | 2021.2.1 | TE0820-test_board-vivado_2021.2-build_17_20220928065907.zip TE0820-test_board_noprebuilt-vivado_2021.2-build_17_20220928065907.zip | Manuela Strücker |
|
2022-09-12 | 2021.2.1 | TE0820-test_board-vivado_2021.2-build_15_20220912132233.zip TE0820-test_board_noprebuilt-vivado_2021.2-build_15_20220912132233.zip | Manuela Strücker |
|
2022-01-28 | 2021.2 | TE0820-test_board-vivado_2021.2-build_11_20220128090819.zip TE0820-test_board_noprebuilt-vivado_2021.2-build_11_20220128090819.zip | Manuela Strücker |
|
2022-01-24 | 2021.2 | TE0820-test_board-vivado_2021.2-build_10_20220124111148.zip TE0820-test_board_noprebuilt-vivado_2021.2-build_10_20220124111148.zip | John Hartfiel |
|
2022-01-14 | 2021.2 | TE0820-test_board-vivado_2021.2-build_8_20220114123035.zip TE0820-test_board_noprebuilt-vivado_2021.2-build_8_20220114123035.zip | John Hartfiel |
|
2021-06-01 | 2020.2 | TE0820-test_board-vivado_2020.2-build_5_20210601084124.zip TE0820-test_board_noprebuilt-vivado_2020.2-build_5_20210601092528.zip | John Hartfiel |
|
2020-04-08 | 2019.2 | TE0820-test_board_noprebuilt-vivado_2019.2-build_10_20200408073458.zip TE0820-test_board-vivado_2019.2-build_10_20200408073444.zip | John Hartfiel |
|
2020-03-25 | 2019.2 | TE0820-test_board_noprebuilt-vivado_2019.2-build_8_20200325083817.zip TE0820-test_board-vivado_2019.2-build_8_20200325083750.zip | John Hartfiel |
|
2020-01-22 | 2019.2 | TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200122154341.zip TE0820-test_board-vivado_2019.2-build_3_20200122154318.zip | John Hartfiel |
|
2020-01-14 | 2019.2 | TE0820-test_board-vivado_2019.2-build_3_20200114081551.zip TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200114081612.zip | John Hartfiel |
|
2019-12-19 | 2019.2 | TE0820-test_board-vivado_2019.2-build_1_20191219075647.zip TE0820-test_board_noprebuilt-vivado_2019.2-build_1_20191219080228.zip | John Hartfiel |
|
2019-10-29 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_09_20191029071045.zip TE0820-test_board-vivado_2018.3-build_09_20191029071028.zip | John Hartfiel |
|
2019-08-09 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_07_20190809084040.zip TE0820-test_board-vivado_2018.3-build_07_20190809083901.zip | John Hartfiel |
|
2019-06-19 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_06_20190619073300.zip TE0820-test_board-vivado_2018.3-build_06_20190619073243.zip | John Hartfiel |
|
2019-04-01 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_03_20190401130135.zip TE0820-test_board-vivado_2018.3-build_03_20190401130123.zip | John Hartfiel |
|
2019-02-21 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_01_20190221103025.zip | John Hartfiel |
|
2018-10-31 | 2018.2 | TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip | John Hartfiel |
|
2018-09-12 | 2018.2 | TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20180912094615.zip TE0820-test_board-vivado_2018.2-build_03_20180912094558.zip | John Hartfiel |
|
2018-08-15 | 2018.2 | TE0820-test_board-vivado_2018.2-build_01_20180706212937.zip TE0820-test_board_noprebuilt-vivado_2018.2-build_01_20180706212952.zip | John Hartfiel |
|
2018-06-19 | 2017.4 | TE0820-test_board-vivado_2017.4-build_10_20180619160713.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180619160728.zip | John Hartfiel |
|
2018-05-24 | 2017.4 | TE0820-test_board-vivado_2017.4-build_10_20180524151356.zip | John Hartfiel |
|
2018-04-25 | 2017.4 | TE0820-test_board-vivado_2017.4-build_07_20180425134435.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_07_20180425134459.zip | John Hartfiel |
|
2018-02-06 | 2017.4 | TE0820-test_board-vivado_2017.4-build_06_20180206203359.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_06_20180206203414.zip | John Hartfiel |
|
2018-02-01 | 2017.4 | TE0820-test_board-vivado_2017.4-build_05_20180201084319.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180201094724.zip | John Hartfiel |
|
2018-01-24 | 2017.4 | TE0820-test_board-vivado_2017.4-build_05_20180124085247.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180124085303.zip | John Hartfiel |
|
2017-11-21 | 2017.2 | TE0820-test_board-vivado_2017.2-build_05_20171121160552.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171121160606.zip | John Hartfiel |
|
2017-11-20 | 2017.2 | TE0820-test_board-vivado_2017.2-build_05_20171120162931.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171120162851.zip | John Hartfiel |
|
2017-10-19 | 2017.2 | TE0820-test_board-vivado_2017.2-build_05_20171019104824.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171019104837.zip | John Hartfiel |
|
Release Notes and Know Issues
Issues | Description | Workaround | To be fixed version |
---|---|---|---|
Xilinx Software | Incompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Request | use corresponding board files for the Vivado versions | -- |
Uboot did not start | Effected Design: TE0820-test_board-vivado_2020.2-build_5_20210601084124.zip TE0820-test_board_noprebuilt-vivado_2020.2-build_5_20210601092528.zip | Use older version, this will be fixed as soon as possible | Solved with 2220124 update |
Flash access on Linux | Device tree is not correct on Linux | add compatibility to "compatible “jedec,spi-nor”" | Solved with 20180524 update |
USB UART Terminal is blocked / SDK Debugging is blocked | This happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager. | Do not use HW Manager connection, or if debugging is necessary:
| Solved with 20180206 update |
Requirements
Software
Software | Version | Note |
---|---|---|
Vitis | 2021.2.1 | needed, Vivado is included into Vitis installation |
PetaLinux | 2021.2 | needed |
SI ClockBuilder Pro | --- | optional |
Hardware
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|---|---|---|---|---|---|---|
Not longer supported by vivado | |||||||
TE0820-03-04EV-1EA | 4ev_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA |
TE0820-03-02CG-1EA | 2cg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA |
TE0820-03-02EG-1EA | 2eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA |
TE0820-03-02EG-1EL | 2eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | 2.5 mm connectors | NA |
TE0820-03-03CG-1EA | 3cg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA |
TE0820-03-04CG-1EA | 4cg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA |
TE0820-03-03EG-1EA | 3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA |
TE0820-03-03EG-1EL | 3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | 2.5 mm connectors | NA |
TE0820-03-2AI21FA | 2cg_1i_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-2BE21FL* | 2eg_1e_2gb | REV03 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA |
TE0820-03-3AI210A | 3cg_1i_2gb | REV03 | 2GB | 128MB | 0GB | NA | NA |
TE0820-03-3BE21FA | 3eg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-3BE21FL | 3eg_1e_2gb | REV03 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA |
TE0820-03-02CG-1ED | 2cg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-2AE21FA | 2cg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-2BE21FA | 2eg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-3AE21FA | 3cg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-3AI21FA | 3cg_1i_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-4AE21FA | 4cg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-4DE21FA | 4ev_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-4DI21FA | 4ev_1i_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-4DE21FL | 4ev_1e_2gb | REV03 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA |
TE0820-03-4DE21FC | 4ev_1e_2gb | REV03 | 2GB | 128MB | 8GB | without encryption NCNR | NA |
TE0820-03-4AI21FI | 4cg_1i_x_2gb | REV03 | 2GB | 128MB | 8GB | without ETH PHY | NA |
TE0820-03-5DR21FA | 5ev_1q_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-2BI21FA | 2eg_1i_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-03-2BI21FL | 2eg_1i_2gb | REV03 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA |
TE0820-03-5DI21FA | 5ev_1i_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-2AE21FA | 2cg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-2AI21FA | 2cg_1i_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-2BE21FA | 2eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-2BE21FAJ | 2eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | without spacers | NA |
TE0820-04-2BE21FL | 2eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA |
TE0820-04-2BE21-V1 | 2eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | Customised |
TE0820-04-2BI21FA | 2eg_1i_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-2BI21FL | 2eg_1i_2gb | REV04 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA |
TE0820-04-3AE21FA | 3cg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-3AI21FA | 3cg_1i_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-3AI21FAT | 3cg_1i_2gb | REV04 | 2GB | 128MB | 8GB | NA | Customer supplied |
TE0820-04-3BE21FA | 3eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-3BE21FL | 3eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA |
TE0820-04-3BE21KA | 3eg_1e_2gb | REV04 | 2GB | 128MB | 64GB | NA | NA |
TE0820-04-4AE21FA | 4cg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-4AI21FI | 4cg_1i_x_2gb | REV04 | 2GB | 128MB | 8GB | without ETH PHY | NA |
TE0820-04-4BI21KL | 4eg_1i_2gb | REV04 | 2GB | 128MB | 64GB | 2.5 mm connectors | NA |
TE0820-04-4DE21FA | 4ev_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-4DE21FL | 4ev_1e_2gb | REV04 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA |
TE0820-04-4DI21FA | 4ev_1i_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-5DI21FA | 5ev_1i_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-5DR21FA | 5ev_1q_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-3BE21ML | 3eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | 2.5 mm connectors | Other EMMC mfr |
TE0820-04-4DE21MA | 4ev_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | Other EMMC mfr |
TE0820-04-4DI21MA | 4ev_1i_2gb | REV04 | 2GB | 128MB | 8GB | NA | Other EMMC mfr |
TE0820-04-S002 | 3eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | Other EMMC mfr|Custom supplied TE0820-04-3BE21MA |
TE0820-04-S005 | 4cg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | Other EMMC mfr|Custom supplied TE0820-04-4AE21MA |
TE0820-04-S004 | 2eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | CAO |
TE0820-04-2BE21MA | 2eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-S006 | 4ev_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | CAO:Other EMMC mfr |
TE0820-04-2BI21ML | 2eg_1i_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-S002C1 | 2eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | CAO |
TE0820-04-S003 | 3eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | 2.5 mm connectors | Other EMMC mfr |
TE0820-04-S009 | 3eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | 2.5 mm connectors | Other EMMC mfr |
TE0820-04-S010 | 4ev_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | Other EMMC mfr |
TE0820-04-4AE21MA | 4cg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
TE0820-04-2BE21MAJ | 2eg_1e_2gb | REV04 | 2GB | 128MB | 8GB | NA | NA |
*used as reference
Design supports following carriers:
Carrier Model | Notes |
---|---|
TE0701 |
|
TE0703 |
|
TE0705 |
|
TE0706* |
|
TEBA0841 |
|
*used as reference
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct type |
XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
Cooler | It's recommended to use cooler on ZynqMP device |
Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
Type | Location | Notes |
---|---|---|
Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts |
Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
PetaLinux | <project folder>\os\petalinux | PetaLinux template with current configuration |
Additional Sources
Type | Location | Notes |
---|---|---|
SI5338 | <project folder>\misc\Si5338 | SI5338 Project with current PLL Configuration |
init.sh | <project folder>\sd\ | Additional Initialization Script for Linux |
Prebuilt
File | File-Extension | Description |
---|---|---|
BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Boot Script-File | *.scr | Distro Boot Script file |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")
_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
_create_win_setup.cmd/_create_linux_setup.sh------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")TE::hw_build_design -export_prebuilt
Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
- Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, u-boot.dtb,system.dtb , bl31.elf, image.ub, z and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Generate Programming Files with Vitis
run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Launch
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Note: Folder "<project folder>/_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub, and boot.scr on SD or USB.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
run on Vivado TCL (Script programs BOOT.bin on QSPI flash)TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0820 (optional)
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
- Copy image.ub, and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to QSPI-Boot and insert SD or USB.
- Depends on Carrier, see carrier TRM.
SD-Boot mode
- Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used.
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scrPower On PCB
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Note: Wait until Linux boot finished
You can use Linux shell now.
i2cdetect -y -r 0 (check I2C 0 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check)
Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- Webserver to get access to Zynq
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Control:
- User LED (PCB REV03 and newer)
- User LED (PCB REV03 and newer)
- Monitoring:
- SI5338_CLK0 Counter:
- Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz - SI5338 CLK is configured to 200MHz by default.
- Set radix from VIO signals to unsigned integer.
- SI5338_CLK0 Counter:
PCB REV03 Design:
- User LED, see: TE0820 CPLD#LED
![](/download/attachments/43680892/image2018-7-6_12-49-48.png?version=1&modificationDate=1530874186000&api=v2)
System Design - Vivado
Block Design
PCB REV03
PS Interfaces
Activated interfaces:
Type | Note |
---|---|
DDR | |
QSPI | MIO |
SD0 | MIO |
SD1 | MIO |
I2C0 | MIO |
UART0 | MIO |
GPIO0 | MIO |
SWDT0..1 | |
TTC0..3 | |
GEM3 | MIO |
USB0 | MIO, USB2 only |
Constrains
Basic module constrains
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design
Design specific constrain
set_property PACKAGE_PIN K9 [get_ports {SI5338_CLK0_D_clk_p[0]}] set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}] set_property DIFF_TERM TRUE [get_ports {SI5338_CLK0_D_clk_p[0]}] set_property PACKAGE_PIN H1 [get_ports {x0[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}] set_property PACKAGE_PIN J1 [get_ports {x1[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}]
Software Design - Vitis
For Vitis project creation, follow instructions from:
Application
Template location: "<project folder>\sw_lib\sw_apps\"zynqmp_fsbl
TE modified 2021.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash (seems to be obsolete and will be removed in one of the next revisions)
TE modified 2021.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0820
Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
- generate u-boot.dtb:
- CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
- CONFIG_SYS_I2C_EEPROM_ADDR=0x50
- CONFIG_ENV_OVERWRITE=y
- Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
Change platform-top.h:
#include <configs/xilinx_zynqmp.h>#no changes
Device Tree
/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /*------------------ QSPI -------------------- */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { //compatible = "flash name, "micron,m25p80"; compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /*-------------------- SD0 eMMC ----------------*/ &sdhci0 { // disable-wp; no-1-8-v; }; /*-------------------- SD1 sd2.0 ----------------*/ &sdhci1 { disable-wp; no-1-8-v; }; /*-------------------- ETH ----------------*/ &gem3 { status = "okay"; ethernet_phy0: ethernet-phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <1>; }; }; /*-------------------- USB 2.0 only ----------------*/ &dwc3_0 { status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /delete-property/phy-names; /delete-property/phys; /delete-property/snps,usb3_lpm_capable; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; &usb0 { status = "okay"; /delete-property/ clocks; /delete-property/ clock-names; clocks = <0x3 0x20>; clock-names = "bus_clk"; }; /*-------------------- I2C ----------------*/ &i2c0 { eeprom: eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; };
/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /*------------------ QSPI -------------------- */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { //compatible = "flash name, "micron,m25p80"; compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /*-------------------- SD0 eMMC ----------------*/ &sdhci0 { // disable-wp; no-1-8-v; }; /*-------------------- SD1 sd2.0 ----------------*/ &sdhci1 { disable-wp; no-1-8-v; }; /*-------------------- ETH ----------------*/ &gem3 { status = "okay"; ethernet_phy0: ethernet-phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <1>; }; }; /*-------------------- USB 2.0 only ----------------*/ &dwc3_0 { status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /delete-property/phy-names; /delete-property/phys; /delete-property/snps,usb3_lpm_capable; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; &usb0 { status = "okay"; /delete-property/ clocks; /delete-property/ clock-names; clocks = <0x3 0x20>; clock-names = "bus_clk"; }; /*-------------------- I2C ----------------*/ &i2c0 { eeprom: eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; };
Kernel
Start with petalinux-config -c kernel
Changes:
Only needed to fix JTAG Debug issue:
CONFIG_CPU_IDLE is not set
CONFIG_CPU_FREQ is not set
- CONFIG_EDAC_CORTEX_ARM64=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- for web server app:
- CONFIG_busybox-httpd=y
- For additional test tools only:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.webfwu
Webserver application suitable for Zynq access. Need busybox-httpd
Additional Software
SI5338
File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"
General documentation how you work with these project will be available on Si5338
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | Authors | Description |
---|---|---|---|
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] | Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] | Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] |
|
2022-09-12 | v.73 | Manuela Strücker |
|
2022-09-06 | v.72 | Manuela Strücker |
|
2022-01-26 | v.70 | John Hartfiel |
|
2022-01-24 | v.68 | John Hartfiel |
|
2022-01-21 | v.67 | John Hartfiel |
|
2022-01-14 | v.66 | John Hartfiel |
|
2021-06-09 | v.65 | Manuela Strücker |
|
2021-06-01 | v.64 | John Hartfiel |
|
2020-05-07 | v.62 | John Hartfiel |
|
2020-04-08 | v.61 | John Hartfiel |
|
2020-03-25 | v.60 | John Hartfiel |
|
2020-01-21 | v.59 | John Hartfiel |
|
2020-01-14 | v.58 | John Hartfiel |
|
2019-12-19 | v.57 | John Hartfiel |
|
2019-10-29 | v.56 | John Hartfiel |
|
2019-08-09 | v.55 | John Hartfiel |
|
2019-06-19 | v.54 | John Hartfiel |
|
2019-04-01 | v.53 | John Hartfiel |
|
2018-09-21 | v.47 | John Hartfiel |
|
2018-10-31 | v.43 | John Hartfiel |
|
2018-09-12 | v.41 | John Hartfiel |
|
2018-07-11 | v.40 | John Hartfiel |
|
2018-07-06 | v.38 | John Hartfiel |
|
2018-06-19 | v.34 | John Hartfiel |
|
2018-02-13 | v.29 | John Hartfiel |
|
2018-02-06 | v.27 | John Hartfiel |
|
2018-01-29 | v.26 | John Hartfiel |
|
2018-01-24 | v.25 | John Hartfiel |
|
2018-01-10 | v.24 | John Hartfiel |
|
2017-12-20 | v.23 | John Hartfiel |
|
2017-11-21 | v.19 | John Hartfiel |
|
2017-11-20 | v.18 | John Hartfiel |
|
2017-11-13 | v.16 | John Hartfiel |
|
2017-11-06 | v.15 | John Hartfiel |
|
2017-10-23 | v.13 | John Hartfiel |
|
2017-10-19 | v.9 | John Hartfiel |
|
2017-09-11 | v.1 | Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] | Initial release |
All | Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] |
Legal Notices
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
Limitation of Liability
In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.
Copyright Notice
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
Environmental Protection
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH, RoHS and WEEE
REACH
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
Error rendering macro 'page-info'
Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]
Table of contents
- No labels