TE USB FX2 Module Configuration

This section describes how to configure the TE USB FX2 module and access some of its resources.

To program the firmware in the EEPROM, the IIC bus should be correctly configured.

To program the bitstream in the Flash, the SPI bus should be correctly configured.

TE USB FX2 modules can be configured through a host computer with the following system requirements:

Configuration mode connections available to the user

TE USB FX2 module type	Configuration mode connections
TE0630
TE0320
TE0300

Configuration modes overview: FPGA bitstream only.

USB interface

TE USB FX2 module is equipped with a Cypress EZ-USB FX2 controller (TE USB FX2 microcontroller) to provide a high-speed USB 2.0 interface. Configuration of the TE USB FX2 module through a USB host is recommended for non-volatile on-site operations such as firmware upgrade or SPI Flash bitstream download.

Even when USB connector is used to program the FPGA image (aka FPGA bitstream), the SPI bus and the the SPI Flash memory are also used by C#  OpenFutNet or Python Open_FUT.

 The procedure followed by one of the two TE programs (or by a custom user program) is the following:

• erase the SPI Flash (FLASH_ERASE command);
• writes the bitstream image in the SPI Flash (FLASH_WRITE command) and readback the bytes written (FLASH_READ command) for integrity check; 
• after SPI Flash writing is complete and checked, the FPGA is powered off (POWER command with command[1]=0) and then on (POWER command with command[1]=1);
• at power on the FPGA automatically read the SPI Flash content to configure itself;
• waits some seconds (2 to 10 seconds) the end of  FPGA configuartion;the FX2 microcontroller's firwmare is able to read the DONE PIN status from PD2 pin (IOD2)
• a READ_STATUS command should be used to check if DONE PIN (reply[4] = EP1INBUF[4] = sts_booting) is high (reply[4]=1) .

Even when USB connector is used to program the FX2 microcontroller's firmware, the IIC bus and the the IIC EEPROM memory are also used by C#  OpenFutNet or Python Open_FUT.

Jtag Interface

The JTAG interface allows a

• fast (10 seconds), frequent but volatile configuration (only the FPGA is programmed using Xilinx ISE or EDK and a .bit bitstream and not the SPI Flash) of the TE USB FX2 module.
• medium-fast (1-2 minutes) non-volatile on-site operations such as SPI Flash bitstream download: indirect SPI in-system programming (ISP).

Only through the JTAG interface it is possible to develop and debug with Xilinx tools (e.g. Xilinx SDK debug,Xilinx ChipScope, Xilinx Microprocessor Debugger).

SPI Interface

SPI interfaces allows a medium-fast (1-2 minutes), frequent and non-volatile configuration (SPI Flash bitstream download) of the TE0300 module (through J3 and direct SPI programming or TE USB FX2 microcontroller and OpenFutNet), TE0320 module (through B2B connection or TE USB FX2 microcontroller and OpenFutNet), TE0630 module (through TE USB FX2 microcontroller and OpenFutNet).

B2B Interface

Through B2B interface JTAG and/or SPI interface could be used (see the two paragraphes above).

It is also possible to use B2B interface for 

• Slave Paralellel (SelectMAP)
• Slave Serial

configurations.

Interface Available to FX2 microcontroller

The FX2 microcontroller uses 4 interfaces (see here):

• USB interface (to USB connector): connection with the host computer;
• I²C interface (to EEPROM): the I²C interface connects the USB controller to the EEPROM chip, which stores vendor ID and device ID and the USB firmware. See chapter DIP Switch for available options.
• SPI interface (to FPGA and Flash): the SPI interface is used to communicate with the FPGA and to access the SPI serial Flash chip. The SPI interface allows a medium-fast (1-2 minutes), frequent and non-volatile configuration (SPI Flash bitstream download) through TE USB FX2 microcontroller and OpenFutNet;
• B2B interface;
• FIFO interface (to FPGA): the FIFO interface provides a high-speed communication channel with the FPGA.The interface can transfer up to 48 MB/s burst rate.