Table of Contents
The Trenz Electronic TEI0015 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.
Intel® MAX 10 Commercial [10M08SAU169C8G]
Speed Grade: C8 (Slowest)
Temperature: 0°C to 85°C
Package compatible device 10M08...10M16 as assembly variant on request possible
SDRAM Memory up to 32 Mbyte (8Mbyte default)
USB 2.0 Multipurpose UART/FIFO IC (FT2232H)
- 4 Kbit EEPROM Memory for FTDI configuration data
- Micro USB Receptacle (communication and power)
SPI Flash - NOT INSTALLED (only special option)
- 8x User LED
- 18 Bit 2MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface: 23x GPIO - Arduino MKR compatible
Power Supply: 5V
Dimension: 86.5mm x 25mm
SMA Connector, J5...6
Amplifier, U12 - U14 - U6
Voltage Reference, U8
Analog to Digital Converter, U15
Voltage Regulator, U10 - U13 - U16
Switching Voltage Regulator/LDO, U11 - U4
SDRAM Memory, U2
- Intel® MAX 10 FPGA, U1
SPI Flash Memory, U5
12.00 MHz MEMS oscillator, U7
FTDI USB2 to JTAG/UART adapter, U3
User LEDs, D2...9
FTDI configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-on LED (Green), D1
Push button, S1...2
Micro USB Connector, J9
1x14 pin header, J2 (Not assembled)
1x6 pin header, J4 (Not assembled)
1x4 Header, J3 (Not assembled)
1x14 pin header, J1 (Not assembled)
Initial Delivery State
Storage device name
Quad SPI Flash
The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.
FPGA Reconfigration can be triggered by pressing push button S1.
|Push Button||Pin Header||Note|
|S1||J2||Connected to nCONFIG|
Signals, Interfaces and Pins
I/Os on Pin Headers and Connectors
|FPGA Bank||Connector Designator||I/O Signal Count||Voltage Level||Notes|
|Bank 1B||J4||5||3.3V||JTAG interface|
FPGA I/O Banks
|FPGA Bank||I/O Signal Count||Connected to||Notes|
|Bank 1A||7||1x14 Pin header, J1||AIN0...6|
|Bank 1B||5||1x6 Pin header, J4||JTAG_EN, TDI, TDO, TMS, TCK|
|Bank 2||4||1x14 Pin header, J1||D2...5|
|5||A2D, U15||ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV|
|1||12MHz Oscillator, U7||CLK12M|
|2||Amplifier, U12||nIAMP_A0, nIAMP_A1|
|Bank 3||22||SDRAM, U2||RAM_ADDR_CMD|
1x14 Pin header, J2
|2||1x14 Pin header, J1||DIO0...1|
|Bank 6||16||SDRAM, U2||DQ0...15|
|Bank 8||8||User Red LEDs, D2...9||LED0...7|
|6||SPI Flash, U5||F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn|
|1||Red LED, D10||CONF_DONE|
|6||FTDI JTAG/UART Adapter, U3||BDBUS0...5|
|1||Push Button, S2||USER_BTN|
The Micro-USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that FTDI USB drivers are installed on your host PC.
FTDI FT2232H U3, DP pin
FTDI FT2232H U3, DM pin
JTAG access to the TEI0015 SoM through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.
Pin Header Connector
|JTAG_EN||J4-2||Pulled-up to 3.3V|
TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
|SDRAM I/O Signals|
Signal Schematic Name
A0 ... A13
|Bank address inputs|
BA0 / BA1
DQ0 ... DQ15
DQM0 ... DQM1
Row Address Strobe
Column Address Strobe
|WE||bank 3||Write Enable|
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG. Channel B is configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.
The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.
|FTDI Chip U3 Pin||Signal Schematic Name||Connected to||Notes|
|ADBUS0||TCK||FPGA bank 1B, pin G2||JTAG interface|
|ADBUS1||TDI||FPGA bank 1B, pin F5|
|ADBUS2||TDO||FPGA bank 1B, pin F6|
FPGA bank 1B, pin G1
|BDBUS0||BDBUS0||FPGA bank 8, pin A4||User configurable|
|BDBUS1||BDBUS1||FPGA bank 8, pin B4||User configurable|
|BDBUS2||BDBUS2||FPGA bank 8, pin B5||User configurable|
|BDBUS3||BDBUS3||FPGA bank 8, pin A6||User configurable|
|BDBUS4||BDBUS4||FPGA bank 8, pin B6||User configurable|
|BDBUS5||BDBUS5||FPGA bank 8, pin A7||User configurable|
|BDBUS6||BDBUS6||FPGA bank 6, pin C11|
|BDBUS7||BDBUS7||FPGA bank 3, pin J7|
|BCBUS0||BCBUS0||FPGA bank 5, pin J9|
|BCBUS1||BCBUS1||FPGA bank 3, pin K5|
|BCBUS2||BCBUS2||FPGA bank 3, pin L4|
|BCBUS3||BCBUS3||FPGA bank 3, pin L5|
|BCBUS4||BCBUS4||FPGA bank 3, pin N12|
Optional SPI flash device maybe assembled in custom variants, normally it is not populated.
|Signal Schematic Name||Connected to||Notes|
|F_CS||FPGA bank 8, pin B3||Chip select|
|F_CLK||FPGA bank 8, pin A3||Clock|
|F_DI||FPGA bank 8, pin A2||Data in / out|
FPGA bank 8, pin C4
|Data in / out, configuration dual-purpose pin of FPGA|
|DEVCLRN||FPGA bank 8, pin B9||Data in / out, configuration dual-purpose pin of FPGA|
|F_DO||FPGA bank 8, pin B2||Data in / out|
The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.
|FTDI U3, Pin EECS|
|EECLK||FTDI U3, Pin EECLK|
|EEDATA||FTDI U3, Pin EEDATA|
The TEI0015 board is equipped with the Analog Devices AD4003BCPZ-RL7 18-bit 2MSPS ADC.
|Diff Amplifier U14, VOUT-|
|IN-||Diff Amplifier U14, VOUT+|
|SDI||FPGA, bank 2, pin M2, ADC_SDI|
|SDO||FPGA, bank 2, pin M1, ADC_SDO|
|SCK||FPGA, bank 2, pin N3, ADC_SCK|
|CNV||FPGA, bank 2, pin N2, ADC_CNV|
|Designator||Color||Connected to||Active Level||Note|
|D2...9||Red||LED1...8||Active High||User LEDs|
|D10||Red||CONF_DONE||Active Low||Configuration DONE LED|
|D1||Green||3.3V||Active High||After power on it will be on.|
|S2||USER_BTN||User push button||Connected to FPGA Bank 8.|
|Clock Source||Schematic Name||Frequency||Note|
|MEMS Oscillator, U7||CLK12M||12.00 MHz|
Connected to FTDI FT2232 U3, pin 3.
Connected to FPGA SoC bank 2, pin H6.
Power and Power-On Sequence
The module is power supplied from USB (optionally via unpopulated pin header).
|Intel MAX 10 10M08 FPGA||TBD*|
* TBD - To Be Determined
Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.
|Power Rail Name|
|VIN||J2-13||-||Input||5 V - Pin Header|
|-||J9-1||Input||5 V - USB Connector|
Absolute Maximum Ratings
|CH1-, CH1+||Analog input voltage on amplifier U12 pin 1, 10||-30||30||V||AD8251 datasheet|
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
VIN supply voltage (5.0V nominal)
|Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)||-10||10||V||AD8251 datasheet|
Module size: 25 mm × 86.5 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1.22 mm.
Currently Offered Variants
Hardware Revision History
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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