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Overview

Firmware for PCB CPLD with designator U26 : LCMX02-256HC

Feature Summary

  • Power Management
  • Reset
  • CPLD JTAG
  • Boot Mode
  • PUDC
  • ETH
  • LED
  • I2C

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank PowerDescription
LED / LEDout25NONE3.3VINRed LED D3
CONFIGout4NONE1.8VETH config pin
EN1 / EN1in32UP3.3VINB2B Power Enable - Old name from PCB REV04 and earlier : EN1 / EN_SC3
JTAGEN / ---in26---3.3VINJTAG enable for CPLD Firmware update
MODE /MODEin30UP3.3VINB2B Boot Mode Pin- Old name from PCB REV04 and earlier :  MODE /MODE_SC1
MODE0_R / MODE0_Rout12NONE3.3VZynq Boot Mode Pin- Old name from PCB REV04 and earlier : MODE0_R / BOOT_R0
MODE2_R / MODE2_Rout17NONE3.3VZynq Boot Mode Pin- Old name from PCB REV04 and earlier : MODE2_R / BOOT_R2
MODE3_R / MODE3_Rout13NONE3.3VZynq Boot Mode Pin- Old name from PCB REV04 and earlier : MODE3_R / BOOT_R3
MR / MRout10UP3.3VZynq Reset - Old name from PCB REV04 and earlier : MR / POR_B
SPI_SCK_FB/VCFG1out8NONE3.3VOnly for PCB REV05 and later. This pin is connected to MIO8 to change Bank 1 voltage for some applications like boundary scan to test MIOs.
RST / ------9---3.3V/ currently_not_used
NOSEQ / NOSEQinout29UP3.3VINNOSEQ pin- Old name from PCB REV04 and earlier : NOSEQ / NOSEQ_SC4
PG_3V3 / PG_3V3in28UP3.3VINPower Good- Old name from PCB REV04 and earlier :  PG_3V3 / PG_1V5
PG_ALL / PG_ALLin27UP3.3VIN

Power Good -  Old name from PCB REV04 and earlier:  PG_DDR_PWR / PG_1V8

PG_MGT / PG_MGTin11NONE3.3V/ currently_not_used
PGOOD / PGOODinout1UP3.3VINB2B Power Good and additional boot mode pin(JTAG only)- Old name from PCB REV04 and earlier :  PGOOD / STAT_SC2
PHY_LED1in5UP1.8VPHY LED Pin
RESIN / RESINin23UP3.3VINB2B Reset - Old name from PCB REV04 and earlier :  RESIN / nRST_SC0
SCL33 / SCL33in14UP3.3VI2C clock pin- Old name from PCB REV04 and earlier :  SCL33 / SCL
SDA33 / SDA33inout16UP3.3VI2C data pin- Old name from PCB REV04 and earlier :  SDA33 / SDA
X0 / X0out21NONEVCCIO34FPGA Pin K8 - Old name from PCB REV04 and earlier : X0 / XA_SC
X1 / X1out20NONEVCCIO34PUDC FPGA Pin K7- Old name from PCB REV04 and earlier : X1 / XB_SC


Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN pin of CPLD (pin 26) (logical one for CPLD, logical zero for FPGA). This pin is connected to B2B (JM1-pin 89) directly. On the carrier board can be this pin enabled or disabled with a dip switch.

CPLD JTAGEN (B2B JM1-89)Description
0FPGA access
1CPLD access

Power

PGOOD  is  low if PG_3V3 and PG_ALL and EN1 is low otherwise it's high impedance. There is no additional power control.

Reset

POR_B is RESIN and PG_3V3 and PG_ALL and EN1 with some delay.

PUDC

X1 can be changed by changing  PUDC generic parameter in firmware source code. In released zip folder can be found all jed file according to PUDC state options.

Boot Mode

Boot mode can be set either by hardware (dip-switch) on the carrier board or by Linux console. Even after booting you can change the boot mode. After changing the boot mode FPGA is restarted automatically by CPLD. To change boot mode a state machine  continuously monitors the corresponding register that can be change via I2C interface between CPLD and FPGA. After changing this register according to desired boot mode , CPLD will reset FPGA.

Change MethodBoot ModeCPLD PGOOD Pin (B2B Pin JM1-30)CPLD MODE Pin (B2B Pin JM1-32)Description
HardwareJTAG00
Hardware---01
HardwareSD Card10
HardwareQSPI11
Change MethodBoot ModeCommand in Linux consoleCommand in FSBLDescription
SoftwareJTAG
i2cset -y 0 0x20 0x01 0x91
iic_write8(0x20,0x01,0x91)
0x20 is device address. 0x1 is register address.
SoftwareSD Card
i2cset -y 0 0x20 0x01 0x93
iic_write8(0x20,0x01,0x93)

SoftwareQSPI
i2cset -y 0 0x20 0x01 0x92
iic_write8(0x20,0x01,0x92)

ETH

CONFIG is constant zero. PHY_LED1 is connected to X0.


FSBL code

CPLD revision,Boot mode and other features of the board will be shown by FSBL code  while booting.The format of these information are shown in the following:

CPLD RevisionSoftware adjusted boot modeExisted boot modes in the programmed jed FilePUDC ModeCurrent boot modeDescription

Deactive (0)0 (QSPI/SD)Pull-up activated (0)JTAG (0)
Active (1)1 (QSPI/JTAG)Pull-up deactivated (1)QSPI (2)
----2 (JTAG/SD)----SD Card (3)
----3 (default QSPI/JTAG/SD)--------

Boundary scan

To implement boundary scanning (especially after the production of the board is necessary to test all MIOs), MIO bank voltage must be set to a certain value.

For more information refer to the following site :https://support.xilinx.com/s/article/57930?language=en_US

From PCB revision 05 and later MIO8 state can be changed by CPLD. According the following table the MIO bank voltage can be determined for FPGA:

Bank VoltageBank 1 (related pin MIO8)Bank 0 (related pin MIO7)Description
2.5V / 3.3 V00MIO8 is pulled up in module hardware.
MIO7 is pulled down in module hardware.
1.8 V11Default value because of pull up resistor on the board



The bank 0 voltage is determined  in 2.5V / 3.3 V for FPGA by connecting MIO7 to GND. Bank 1 voltage can be determined for FPGA by changing the state of MIO8 in  linux console or in FSBL code:

Bank 1 Voltage Command in linux consoleCommand in FSBL codeDescription
2.5 V / 3.3 V
i2cset -y 0 0x20 0x01 0x61
iic_write8(0x20,0x01,0x61)

Only for boundary scaning
MIO8 is set to low.
In this case FPGA will be reset and boot mode will be set in JTAG mode automatically.

1.8 V
i2cset -y 0 0x20 0x01 0x64
iic_write8(0x20,0x01,0x64)

MIO8 is set to high impedance. Because of pull up resistor on the board MIO8 will be set on high.

As default MIO8 is set to high in the hardware to inform FPGA that  bank 1 voltage is 1.8V. To implement boundary scan it is necessary to change MIO8 state to low. After changing the MIO8 state to low, FPGA will be reset and set in JTAG boot mode by CPLD automatically.

LED

LED stateDescriptionRelated command
Blink sequence   ********Reset is active. (RESIN = '0')Push reset button on the carrier board
ONBoth boot mode and MIO8 state in linux console or in FSBL code are not changed.Default state after turning on
Blink sequence   ****ooooBoot mode is changed by software either in linux console or by FSBL code.
i2cset -y 0 0x20 0x01 0x91/i2cset -y 0 0x20 0x01 0x92/i2cset -y 0 0x20 0x01 0x93 commands in linux console
Blink sequence   ***oooooMIO8 stateis changed in linux console or in FSBL code.
i2cset -y 0 0x20 0x01 0x61 command in linux console
ON / OFFControlled by user
i2cset -y 0 0x20 0x03 0xa0    → LED OFF
i2cset -y 0 0x20 0x03 0xa1    → LED ON
i2cset -y 0 0x20 0x03 0x00   → LED will not be controlled by user.

Appx. A: Change History and Legal Notices

Revision Changes

  • Changes REV03 to REV04
    • PGOOD is always 'Z', if pg is high. In last version it is valid only , if BOOTMODE_GEN is not equal to 3.

    • LED status is changed from *****ooo state to ON state for default status.

    • LED can be controlled by user. For this purpose user should give the following commands:

      • LED OFF                                         →  i2cset -y 0 0x20 0x03 0xa0
      • LED ON                                          →  i2cset -y 0 0x20 0x03 0xa1
      • LED will not be controlled by user.             →  i2cset -y 0 0x20 0x03 0x00
  • Changes REV02 to REV03
    • Boot mode configuration via hardware (dip switch) and firmware added (Boot mode configuration via linux console)
    • Pullup or pulldown states of PORT pins was checked.
    • Adding i2c to gpio ip (i2c_slave.vhd) 
    • Changing oscillator frequency from 12.09 MHZ to 24.18MHZ
    • PORT signals according to the schematic are renamed.
    • JTAG time constraint correction.
    • PGOOD pin is used as boot mode selector pin.
    • VCFG1 (MIO8) pin can be changed by i2cset command. This pin must be grounded by boundary scanning.

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.


DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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REV04REV05,REV04,REV03

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  • Working in process

2023-06-02

v.14

REV03REV05,REV04,REV03

John Hartfiel

  • Update documentation, IO description and PGOOD

2022-08-08

v.13

REV03REV05,REV04,REV03

Mohsen Chamanbaz 

  • REV03 release
  • Firmware release (SC-PGM-TE0715-030405_SC715-03_20220808.zip)
  • Access to boot mode in linux console
  • Access to MIO8 for boundary scan (only for PCB REV05)
  • Indicating CPLD revision, boot mode and PUDC state while booting

2018-07-17

v.6REV02REV04,REV03John Hartfiel
  • REV02 , Firmware released  2015-08-18
2018-07-16

v.1



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Initial release

All

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Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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