TE0724 TRM

Overview

The Trenz Electronic TE0724 is an industrial-grade SoC module based on Xilinx Zynq-7010, which provides a dual core ARM Cortex A9 and a . It provides a gigabit ethernet transceiver, 1GByte of DDR3L SDRAM, 32 MByte Flash memory as configration and data storage. it includes strong pwerregulators for all needed voltages and a robust high-speed connector for in- and outputs. It has a 6 x 4 cm form factor.

Key Features

• Xilinx Zynq XC7Z010-1CLG400I or XC7Z020-1CLG400I
• Dual-core ARM Cortex-A9 MPCore
• Max. 667 MHz
• Shock proof and vibration resistant
• Size 6 x 4 cm
• Plug-On-Modul with 1 × 160 Pin High-Speed connector
• 1 GByte DDR3L SDRAM
• 32 MByte QSPI Flash Speicher
• 1 x GBit Ethernet PHY
• 1 x MAC-Address EEPROM
• 128 KBit EEPROM
• 1 x CAN Transceiver
• On-Board DC/DC-regulators
• Excellent signal integrity due to well dirstributed supply pins

Additional assembly options are available for cost or performance optimization upon request.

Block Diagramm

Main Components

Table 1: TE0724-02 main components.

1. XILINX ZYNQ XC7Z020-2CLG400C, U1
2. Gigabit Ethernet Transceiver Alaska 88E1512, U7
3. Power Manager Dialog DA9062, U4
4. 1GByte - 2x 4Gbit DDR3L RAM, U3, U5
5. 32MByte Spansion SPI Flash S25FL256, U13
6. 128KByte Serial EEPROM Microchip 24AA, U10
7.  CAN Transceiver MCP2542FDT, U2
8.  160 Pin Samtec B2B Connector ST5-80-1.50-L-D-P-TR, J1

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

Boot mode is selected via two pins at B2B connector J2. By default the TE0724 supports JTAG and SPI Boot Mode. Connecting a SD Card via B2B connector to MIO Pins (See SD Card Interface) gives the possibility to boot from SD Card.

Table 2: Boot mode selection.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector: 

Table 3: General overview of PL I/O signals connected to the B2B connectors.

All PS MIO banks as well as PL bank 34 are powered by on-module DC-DC power rails. Valid VCCO_35 for PL bank 35 should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the PS I/Os MIO40 to MIO51 depend on the carrier board peripherals connected to these pins.

JTAG Interface

JTAG access to the ZYNQ SoC is provided through B2B connector J1 and testpoints.

Table 4: JTAG interface signals.

System Controller Pins

Special purpose pins are available for System Controller functions and are routed to the Power Management IC (U4) with the following default configuration:

Table 5: System Controller CPLD I/O pins.

Quad SPI Interface

Quad SPI Flash (U13) is connected to the Zynq PS QSPI_0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Table 6: Quad SPI interface signals and connections.

SD Card Interface

There is no physical SD Card slot on the module. Three different interface options are possible at a carrier via the PS MIO 10 to 15 or 40 to 45 or 46 to 51 plus additional MIOs for SD Card Detect and Write Protect as well as SD Card Power Controls. For details compare Xilinx UG585-Zynq-7000-TRM Table 2-4.

Ethernet Interface PHY

The TE0724 is equipped with a Marvell Alaska 88E1512 Gigabit Ethernet PHY (U7) connected to PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the PL IO_L11P_T1_SRCC_34.

Table 7: Ethernet PHY connections.

CAN PHY

A felxible data rate CAN Transceiver is provided by a Microchip MCP2542FDT.

I2C Interface

On-board I²C devices are connected to PS MIO28 (SCL) and MIO29 (SDA). I²C addresses for on-board devices are listed in the table below:

Table x: I²C slave device addresses.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

DDR Memory

By default TE0724 module has 2 DDR3L SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U13) on the TE0724-02 is a SPANSION S25FL256S with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

USER EEPROM

A Microchip 24AA128T serial EEPROM (U10) is availabe for e.g. module idetification and user Data. The device has 128Kbit memory with max 64 bytes page write capability. It is accessible over I²C bus with slave device address 0x50.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table : Reference clock signals.

On-board LEDs

Table : On-board LEDs.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table : Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared. <-- What?

Power Distribution Dependencies

Regulator dependencies and max. current.

Put power distribution diagram here...

Figure : Module power distribution diagram.

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Power-On Sequence

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Put power-on diagram here...

Figure : Module power-on diagram.

Voltage Monitor Circuit

If the module has one, describe it here...

Power Rails

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Table : Module power rails.

Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.

Bank Voltages

Table : Module PL I/O bank voltages.

Board to Board Connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Table : Module absolute maximum ratings.

Recommended Operating Conditions

Table : Module recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: ... mm × ... mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: ... mm.

• PCB thickness: ... mm.

• Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Put mechanical drawings here...

Figure : Module physical dimensions drawing.

Revision History

Hardware Revision History

Table : Module hardware revision history.

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Put picture of actual PCB showing model and hardware revision number here...

Figure : Module hardware revision number.

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	John Hartfiel	Rework chapter currently available products
02 Feb 2018	v.60	John Hartfiel	Remove Link to Download
2017-05-30	v.1	Jan Kumann	Initial document.
	all	Jan Kumann, John Hartfiel

Table : Document change history.

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