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Table of Contents
Overview
The Trenz Electronic TE0706 Carrier Board provides functionalities for testing, evaluation and development purposes of company's 4 x 5 cm SoMs. The Carrier Board is equipped with various components and connectors for different configuration setups and needs. The interfaces of the SoM's functional units and PL I/O-banks are connected via board-to-board connectors to the Carrier Board's components and connectors for easy user access.
See "4 x 5 cm carriers" page for more information about supported 4 x 5 cm SoMs.
Key Features
- 3 x Samtec LSHM Series Board to Board Connectors
- VG96 connector (mounting holes and solder pads, J6) and 50-pin IDC male connector socket (J5) for access to PL I/O-bank pins
- Micro SD card socket
- SDIO port expander with voltage-level translation
- USB2.0 type A connector, optionally Micro USB 2.0 connector
- 1 x user-push button S2, by default configured as system reset button
- 1 x RJ45 GbE MagJack J3, connected via MDI to B2B connector JB1
- 1 x Marvell Alaska 88E1512 GbE PHY, providing Ethernet interface in conjunction with RJ45 GbE MagJack J2
- 5V power supply barrel jack
- 4 A High-Efficiency Power SoC DC-DC Step-Down Converter (Enpirion EN6347) for 3.3V power supply
- XMOD JTAG- / UART-header JX1
- DIP-switch S1 to set Som's System Controller CPLD control signals
- 3 x VCCIO selection jumper J10, J11 and J12 to set SoM's PL I/O-bank voltages
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
Figure 1: TE0706-02 block diagram.
Main Components
Figure 2: TE0706-02 Carrier Board
- 5V power connector jack, J1
- Reset switch, S2
- USB2.0 type A receptacle, J7
- Micro SD card socket with Card Detect, J4
- 50 pin IDC male connector, J5
- 1000Base-T Gigabit RJ45 Ethernet MagJack, J3
- 1000Base-T Gigabit RJ45 Ethernet MagJack, J2
- XMOD JTAG- / UART-header, JX1
- User DIP-switch, S1
- VCCIO selection jumper block, J10 - J12
- External connector (VG96) placeholder, J6
- Samtec Razor Beam™ LSHM-150 B2B connector, JB1
- Samtec Razor Beam™ LSHM-150 B2B connector, JB2
- Samtec Razor Beam™ LSHM-130 B2B connector, JB3
Initial Delivery State
Board is shipped in following configuration:
- VCCIO voltage selection jumpers are all set to 1.8 V.
- S2 switch configured as reset button.
- One VG96 connector (not soldered to the board, but included in the package as separate component)
Different delivery configurations are available upon request.
Signals, Interfaces and Pins
B2B Connector
With the TE0706 Carrier Board's Board-to-Board Connectors (B2B) the MIO- and PL I/O-bank's pins and further interfaces of the mounted SoM can be accessed. A large quantity of these I/O's are also usable as LVDS-pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.
Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1, JB2 and JB3:
| B2B Connector | Interfaces | Count of I/O's | Notes |
|---|---|---|---|
| JB1 | User I/O | 48 single ended or 24 differential | - |
| GbE MagJack MDI | 8 | - | |
| SD IO | 6 | - | |
| MIO | 8 | - | |
| SoM control signals | 5 | - | |
| JB3 | GbE PHY RGMII | 18 | - |
| USB2.0 (OTG, device and host mode) | 5 | - | |
| JB2 | User I/O | 18 single ended | - |
| 48 single ended or 24 differential | - | ||
| JTAG | 4 | - | |
| SoM control signals | 1 | - | |
| MagJack J3 LED's | 2 | - |
Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
On-board Connector
The TE0706 Carrier Board has and a 50-pin IDC male connector J5 and soldering pads as place-holder to mount a VG96 connectors J6 to get access the PL I/O-bank's pins and further interfaces of the mounted SoM. With these connectors, SoM's PL-I/O's are available to the user, a large quantity of these I/O's are also usable as differential pairs.
Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the connectors J5 and J6:
| On-board Connector | Control Signals and Interfaces | Count of I/O's | Notes |
|---|---|---|---|
| J5 | User I/O | 18 single ended | - |
| 14 single ended or 7 differential | - | ||
| MIO | 8 | - | |
| MagJack J2 LED's | 2 | - | |
| J6 | User I/O | 82 single ended or 41 differential | - |
| SoM control signals | 2 | 'PGOOD', 'NOSEQ' |
Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.
JTAG Interface
JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.
JTAG Signal | B2B Connector Pin | XMOD Header JX1 | Note |
|---|---|---|---|
| TCK | JB2-100 | JX1-4 | - |
| TDI | JB2-96 | JX1-10 | - |
| TDO | JB2-98 | JX1-8 | - |
| TMS | JB2-94 | JX1-12 | - |
Table 3: JTAG interface signals.
UART Interface
UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:
| UART Signal Schematic Name | B2B | XMOD Header JB3 | Note |
|---|---|---|---|
| MIO14 | JB1-91 | JX1-7 | UART-RX (receive line) |
| MIO15 | JB1-86 | JX1-3 | UART-TX (transmit line) |
Table 4: UART interface signals.
I²C Interface
One of the SoM's I²C interface is routed to the on-board connector J5 and is available to the user for general purposes:
| I²C Signal Schematic Name | B2B | On-board Connector | Note |
|---|---|---|---|
| MIO11 | JB1-94 | J5-27 | I²C data line |
| MIO10 | JB1-96 | J5-28 | I²C clock line |
Table 5: I²C interface signals.
SD IO Interface
The SD IO interface of the mounted SoM is routed to the on-board Texas Instruments TXS02612 SDIO port expander U4. This IC provides a necessary VDD/VCCIO translation between the MicroSD Card socket J4 (3.3V) and the SoM's Zynq device MIO-bank (1.8V):
| SD IO Signal Schematic Name | B2B | Connected to | Note |
|---|---|---|---|
| SD_DAT0 | JB1-24 | U4-6 | SD IO data |
| SD_DAT1 | JB1-22 | U4-7 | SD IO data |
| SD_DAT2 | JB1-20 | U4-1 | SD IO data |
| SD_DAT3 | JB1-18 | U4-3 | SD IO data |
| SD_CLK | JB1-28 | U4-9 | SD IO clock |
| SD_CMD | JB1-26 | U4-4 | SD IO command |
| MIO0 | JB1-88 | J4-9 | Card Detect signal |
Table 6: SD IO interface signals.
USB2.0 Interface
TE0706-02 board has one physical USB2.0 type A socket J7, the differential data signals of the USB2.0 socket are routed to the B2B connector JB3, where they can be accessed by the corresponding USB2.0 PHY transceiver of the mounted SoM.
There is also the option to equip the board with a Micro USB 2.0 type B (receptacle) socket (J8) to the board as alternative fitting option. With this fitting option (Micro USB2.0 type B), the USB2.0 interface can also be used for Device mode, OTG and Host Modes.
For USB2.0 Host mode, the Carrier Board is additionally equipped with a power distribution switch U5 to provide the USB2.0 interface with the USB supply voltage USB-VBUS with nominal value of 5V. OTG mode is not available with USB2.0 Type A socket.
Following table gives an overview of the USB2.0 interface signals:
| USB2.0 Signal Schematic Name | B2B | Connected to | Note |
|---|---|---|---|
| OTG-D_N | JB2-48 | J11-2, (J10-2) | USB2.0 data |
| OTG-D_P | JB2-50 | J11-3, (J10-3) | USB2.0 data |
| OTG-ID | JB2-52 | J11-4 | Ground this pin for A-Device (host), left floating this pin for B-Device (peripheral). |
| VBUS_V_EN | JB2-54 | U3, pin 4 | Enable USB-VBUS. |
| USB-VBUS | JB2-56 | J11-1, (J10-1) | USB supply voltage in Host mode. |
Table 7: USB2.0 interface signals and connections.
Gigabit Ethernet Interface
The TE0706 Carrier Board is equipped with a Marvell Alaska 88E1512 Gigabit Ethernet PHY (U6), which provides in conjunction with the Gigabit Ethernet MagJack J2 a 1000Base-T Ethernet (GbE) interface. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied by on-board 25MHz oscillator (U7).
The GbE MegJack J2 has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) to the GbE PHY.
| PHY U6 pins | B2B-pin | Notes |
|---|---|---|
| ETH-MDC/ETH-MDIO | JB3-49, JB3-51 | - |
| PHY_LED0 | - | Connected to GbE MagJack J2 LED0 (green). Also connected to J5-24 (PHY_LED0_CON). |
| PHY_LED1 | - | Connected to GbE MagJack J2 LED1 (green). Also connected to J5-23 (PHY_LED1_CON). |
| PHY_INT | JB3-33 | - |
| CONFIG | JB3-60 | - |
| CLK125 | JB3-32 | PHY Clock (125 MHz) output. |
| ETH-RST | JB3-53 | - |
| RGMII | JB3-37 - JB-44, JB3-47, JB3-57 - JB-59 | Reduced Gigabit Media Independent Interface. 12 pins. |
| SGMII | - | Serial Gigabit Media Independent Interface. Not connected. |
| MDI | - | Media Dependent Interface. Connected to Gigabit Ethernet MagJack J2. |
Table 8: GbE interface signals and connections.
RJ45 Gigabit Ethernet MagJack J3
The TE0706-02 carrier board is also equipped with a second Gigabit-Ethernet MagJack J3, which is connected via MDI to the B2B connector JB1.
There is usually a corresponding Gigabit Ethernet PHY on 4 x 5 SoMs (e.g. TE0715 or TE0720), which can be used in conjunction with the baseboard MagJack J3.
| GbE PHY Signal Schematic Name | B2B | Connected to | Notes |
|---|---|---|---|
| PHY_MDI0_P | JB1-3 | J3-2 | - |
| PHY_MDI0_N | JB1-5 | J3-3 | - |
| PHY_MDI1_P | JB1-9 | J3-4 | - |
| PHY_MDI1_N | JB1-11 | J3-5 | - |
| PHY_MDI2_P | JB1-15 | J3-6 | - |
| PHY_MDI2_N | JB1-17 | J3-7 | - |
| PHY_MDI3_P | JB1-21 | J3-8 | - |
| PHY_MDI3_N | JB1-23 | J3-9 | - |
| ETH_LED1 | JB2-90 | Green MegJack J3 LED | - |
| ETH_LED2 | JB2-99 | Green MegJack J3 LED | - |
Table 9: RJ45 GbE MagJack signals and connections.
XMOD FTDI JTAG-Adapter Header
The JTAG interface of the mounted SoM can be accessed via XMOD header JX1, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment. So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2.0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.
Following table describes the signals and interfaces of the XMOD header JX1:
| JX1 pin | Signal Schematic Net Name | B2B | Note |
|---|---|---|---|
| C (pin 4) | TCK | JB2-100 | - |
| D (pin 8) | TDO | JB2-98 | - |
| F (pin 10) | TDI | JB2-96 | - |
| H (pin 12) | TMS | JB2-94 | - |
| A (pin 3) | MIO15 | JB1-86 | UART-TX (transmit line) |
| B (pin 7) | MIO14 | JB1-91 | UART-RX (receive line) |
| E (pin 9) | - | - | not used |
| G (pin 11) | - | - | not used |
Table 10: XMOD header signals and connections.
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the mounted SoM's 'VCCJTAG' (pin JB2-92). Set the DIP-switch with the setting:
| XMOD DIP-switches | Position |
|---|---|
| Switch 1 | ON |
| Switch 2 | OFF |
| Switch 3 | OFF |
| Switch 4 | ON |
Table 11: XMOD adapter board DIP-switch positions for voltage configuration.
Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices.
The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.
On-board Peripherals
4-bit DIP-switch
Table below describes DIP-switch S1 settings for configuration of the mounted SoM:
| Switch | Signal Name | ON | OFF | Notes |
|---|---|---|---|---|
| S1-1 | - | - | - | Not connected. |
| S1-2 | PROGMODE | JTAG enabled for programing mounted SoM's Zynq-SoC. | JTAG enabled for programing mounted SoM's SC-CPLD. | - |
| S1-3 | MODE | Drive SoM SC CPLD pin 'MODE' low. | Leave SoM SC CPLD pin 'MODE' open. | Boot mode configuration, if supported by SoM. (Depends also on SoM's SC-CPLD firmware). |
| S1-4 | EN1 | Drive SoM SC CPLD pin 'EN1' low. | Drive SoM SC CPLD pin 'EN1' high. | Usually used to enable/disable FPGA core-voltage supply. (Depends also on SoM's SC CPLD firmware). Note: Power-on sequence will be intermitted if S1-4 is set to OFF and if functionality is supported by SoM. |
Table 12: DIP-switch S1 SoM configuration settings.
Figure 3: User DIP-switch S1
VCCIO Selection Jumper
Note: The corresponding PL I/O-bank supply-voltages of the 4 x 5 SoM to the selectable base-board voltages VCCIOA, VCCIOB and VCCIOC are depending on the mounted 4 x 5 SoM and varying in order of the used model.
Refer to the SoM's schematic for information about the specific pin assignments on module's B2B-connectors regarding the PL I/O-bank supply-voltages and to the 4 x 5 Module integration Guide for VCCIO voltage options.
The Carrier Board VCCIO for the PL I/O-banks of the mounted SoM are selectable by the jumpers J10, J11 and J12.
Following table describes how to configure the VCCIO of the SoM's PL I/O-banks with jumpers:
| Supply Voltage by Jumper | Supply Voltage by 0-Ohm Resistor | Supply Voltage by Connector J6 | ||||
|---|---|---|---|---|---|---|
| Voltage Level | 1.8V | 3.3V | 1.8V | 3.3V | Variable | |
| VCCIOA | J10: 1-2, 3 | J10: 1, 2-3 | - | R20 | J6 pin B32 | |
| VCCIOB | J11: 1-2, 3 | J11: 1, 2-3 | R29 | R21 | - | |
| VCCIOC | J12: 1-2, 3 | J12: 1, 2-3 | R30 | R22 | J6 pin B1 | |
Table 13: VCCIO jumper settings.
Figure 4: Base-board supply-voltages (VCCIOA, VCCIOB, VCCIOC) selection jumpers.
Only one supply-source is allowed to configure the base-board supply-voltages, either by jumper, by 0-Ohm-resistor or by connector J6. If a supply-voltage is configured by 0-Ohm-resistor or connector J6, then the corresponding configuration-jumper has to be removed. There aren't 0-Ohm-resistors and supply-voltages by connector J6 allowed if the corresponding base-board supply-voltage is configured by jumper. Vice versa jumpers and 0-Ohm-resistors have to be removed if supplying corresponding base-board supply-voltage by connector J6.
Note: If supplying base-board supply-voltages by connector J6, the module's internal 3.3V voltage-level on pins 9 and 11 of B2B-connector JB2 has to be reached stable state.
Take care of the VCCO voltage ranges of the particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges.
It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM.
RTC Buffer Voltage Supply Header
The buffer voltage of the SoM's RTC can be supplied through the header J9 (VBAT-pin). Refer to the SoM's TRM for recommended voltage range and absolute maximum ratings.
Push Button
The Carrier Board's push button S2 is connected to the 'RESIN' signal, the function of the button is to trigger a reset of the mounted SoM by driving the reset-signal 'NRST_IN' to ground.
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U6) is provided with Marvell Alaska 88E1512. The Ethernet PHY RGMII interface is connected to the B2B connector JB3, where they can be accessed by the mounted SoM's PS bank. Reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U7), the 125MHz output clock signal *CLK125' is connected to the B2B connector pin JB3-32.
SDIO Port Expander
The TE0706 Carrier Board is equipped with a Texas Instruments TXS02612 SDIO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and the PS MIO-bank of the Zynq device of the mounted SoM. The Micro SD Card has 3.3V signal voltage level, but the PS MIO-bank on the Xilinx Zynq module has VCCIO of 1.8V.
Power and Power-On Sequence
Power Consumption
The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq device.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
| Power Input | Typical Current |
|---|---|
| 5VIN | TBD* |
Table 14: Typical power consumption.
* TBD - To Be Determined soon with reference design setup.
Power supply with minimum current capability of 3A for system startup is recommended.
To avoid any damage to the module, check for stabilized on-board voltages and VCCIO's before put voltages on PL I/O-banks and interfaces. All I/Os should be tri-stated during power-on sequence.
Power Distribution Dependencies
The Carrier Board needs one single power supply voltage with a nominal value of 5V. Following diagram shows the distribution of the input voltage '5VIN' to the on-board components on the mounted SoM:
Figure 5: Board power distribution diagram.
Power Rails
The voltage direction of the power rails is from board and on-board connectors' view:
| Module Connector (B2B) Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| JB1 | 3.3V | Out | 2, 4, 6, 14, 16 | 3.3V module supply voltage |
| VCCIOA | Out | 10, 12 | PL IO-bank VCCIO | |
| M1.8VOUT | In | 40 | 1.8V module output voltage | |
| VBAT | Out | 80 | RTC buffer voltage | |
| JB2 | 1.8V | Out | 2, 4 | 1.8V module supply voltage |
| VCCIOB | Out | 6 | PL IO-bank VCCIO | |
| VCCIOC | Out | 8, 10 | PL IO-bank VCCIO | |
| M3.3VOUT | In | 9, 11 | 3.3V module output voltage | |
| VCCJTAG | In | 92 | 3.3V JTAG VCCIO | |
| JB3 | USB-VBUS | Out | 56 | USB Host supply voltage |
Table 15: Power pin description of B2B module connector.
| On-board Connector Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| J5 | 3.3V | Out | 6, 45 | 3.3V module supply voltage |
| M3.3VOUT | In | 5, 46 | 3.3V module output voltage | |
| J6 | VCCIOA | Out | B32 | PL IO-bank VCCIO |
| VCCIOC | Out | B1 | PL IO-bank VCCIO | |
| M3.3VOUT | In | C32 | 3.3V module output voltage | |
| 3.3V | Out | C31 | 3.3V module supply voltage | |
| 5VIN | In | A1, A2 | Carrier Board supply power |
Table 16: Power Pin description of on-board connector.
| Jumper / Header Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| J10 | VCCIOA | Out | 2 | - |
| 1.8V | Out | 1 | - | |
| M3.3VOUT | Out | 3 | - | |
| J11 | VCCIOB | Out | 2 | - |
| 1.8V | Out | 1 | - | |
| M3.3VOUT | Out | 3 | - | |
| J12 | VCCIOC | Out | 2 | - |
| 1.8V | Out | 1 | - | |
| M3.3VOUT | Out | 3 | - |
Table 17: Power Pin description of VCCIO selection jumper pin header.
| Main Power Jack and Pins Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| J1 | 5VIN | In | - | - |
| J6 | 5VIN | In | A1, A2 | '5VIN' power supply to the Carrier Board as alternative to J1 |
| J9 | VBAT | In | 1 | Attention: Pin 2 connected to ground. VBAT voltage connected on this pin cause short-circuit. |
Table 18: Main Power jack and pins description.
| Peripheral Socket Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| J7 / J8 | USB-VBUS | Out | 1 | USB2.0 Type A socket / Micro USB2.0 B socket |
| J4 | M3.3VOUT | Out | 4 | MikroSD Card socket VDD |
Table 19: Power pin description of peripheral connector.
| XMOD Header Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| JX1 | 3.3V | - | 5 | not connected |
| VIO | Out | 6 | connected to 'VCCJTAG' (pin JB2-92) |
Table 20: Power pin description of XMOD/JTAG Connector.
Board to Board Connectors
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Variants Currently In Production
| Module Variant | Operating Temperature | USB2.0 Socket | Temperature Range |
|---|---|---|---|
| TE0706-02 | -40°C to +85°C | USB2.0 Type A socket fitted | Industrial |
| TE0706-D-02 | -40°C to +85°C | Micro USB2.0 Type B socket fitted | Industrial |
Table 21: Board variants.
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
5VIN supply voltage | -0.3 | 7 | V | MP5010A, EN6347QI, EN5311QI data sheet |
Storage temperature | -55 | +85 | °C | Marvell 88E1512 data sheet |
Table 22: Module absolute maximum ratings.
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| 5VIN supply voltage | 4.75 | 5.25 | V | USB2.0 specification concerning 'VBUS' voltage |
| Operating temperature | -40 | +85 | °C | - |
Table 23: Module recommended operating conditions.
Operating Temperature Ranges
Industrial grade: -40°C to +85°C.
The TE0706 Carrier Board itself is capable to be operated at industrial grade temperature range.
Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.
Physical Dimensions
Board size: PCB 100mm × 64.5mm. Notice that the USB type A socket on the left and the Ethernet RJ-45 jacks on the right are hanging slightly over the edge of the PCB making the total width of the longer side approximately 106mm. Please download the assembly diagram for exact numbers.
Mating height of the module with standard connectors: 8mm
PCB thickness: 1.65mm
Highest parts on the PCB are USB type A socket and the Ethernet RJ-45 jacks, approximately 15mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Figure 6: Board physical dimensions drawing.
Revision History
Hardware Revision History
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| 2016-06-28 | 01 |
| - | TE0706-01 |
| - | 02 |
| - | TE0706-02 |
Table 24: Module hardware revision history.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Figure 7: Board hardware revision number.
Document Change History
Date | Revision | Contributors | Description |
|---|---|---|---|
| Ali Naseri |
| ||
2017-07-06 | v.52 | Ali Naseri, Jan Kumann |
|
| 2017-01-06 | v.1 | Ali Naseri |
|
Table 25: Document change history.
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WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
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