TEB0911 TRM

Overview

The Trenz Electronic TEB0911 UltraRack+ board is an industrial-grade motherboard integrating a Xilinx Zynq Ultrascale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SODIMM socket with 64-bit wide data bus, 24 MGT Lanes and powerful switch-mode power supplies for all on-board voltages.. The motherboard exposes the Zynq MPSoC's pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ MPSoC and for developing purposes. The motherboard is capable to be fitted to a dedicated enclosure. On the enclosure's rear and front panel, I/O's and MGT interfaces are accessible through 6 on-board FMC connectors and other standard high-speed interfaces for USB3.0, SFP+, SSD, GbE, etc.

Key Features

• Single 24V main power supply
• 2x USB3 A Connector (Superspeed Host Port (Highspeed at USB2))
• Gigabit Ethernet RGMII PHY with RJ45 MegJack
• Dual SFP+ Connector (2x1 Cage)
• DDR4-SDRAM SODIMM socket (64bit bus width)
• SSD (Solid State Disk) Connector
• CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
• 1x DisplayPort
• 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x  Microchip 24AA025E48T-I/OT)
• All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
• 6x FMC HPC Connectors
• 6x FMC Fans
• 3x Optional 4-wire PWM fan connectors
• 10 output programmable PLL clock generator Si5345A
• Quad programmable PLL clock generator SI5338A
• 1x SMA coaxial connectors for reference clock signal input
• MicroSD-Socket (bootable)
• 32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
• System Controller CPLD Lattice MachXO2 7000 HC
• 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLD
• On-board DC-DC PowerSoCs and LDOs

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Put your block diagram here...

Figure 1: TE0xxx-xx block diagram.

Main Components

Put top and bottom pics with labels of the real PCB here...

Table 1: TE0xxx-xx main components.

Add description list of PCB labels here...

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:

Table 2: Available boot modes of the on-board Zynq MPSoC

Refer also to the documentation of the SC CPLD firmware of the TEB0911 motherboard.

Signals, Interfaces and Pins

FMC Connectors

The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT Lanes for use by other mezzanine modules and expansion cards.

The connector supports single ended and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.

Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:

Figure x: General overview of the FMC connectors

Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors  A - F:

1. FMC A
2. FMC B
3. FMC C
4. FMC D
5. FMC E
6. FMC F
   

FMC A

FMC A Interfaces:

Table 3: FMC A connector interfaces

FMC A MGT Lanes:

Table 4: FMC A connector MGT lanes

FMC A Clock Signals:

Table 5: FMC A connector clock signal input

FMC A VCC/VCCIO:

Table 6: FMC A connector available VCC/VCCIO

FMC A Cooling Fan:

Table 7: FMC A connector cooling fan

FMC F

FMC F Interfaces:

Table 8: FMC F connector interface

FMC F MGT Lanes:

Table 9: FMC F connector MGT lanes

FMC F Clock Signals:

Table 10: FMC F connector clock signal input

FMC F VCC/VCCIO:

Table 11: FMC F connector available VCC/VCCIO

FMC F Cooling Fan:

Table 12: FMC F connector cooling fan

FMC B

FMC B Interfaces:

Table 13: FMC B connector interfaces

FMC B MGT Lanes:

Table 14: FMC B connector MGT lanes

FMC B Clock Signals:

Table 15: FMC B connector clock signal input

FMC B VCC/VCCIO:

Table 16: FMC B connector available VCC/VCCIO

FMC B Cooling Fan:

Table 17: FMC B connector cooling fan

FMC C

FMC C Interfaces:

Table 18: FMC C connector interfaces

FMC C MGT Lanes:

Table 19: FMC C connector MGT lanes

FMC C Clock Signals:

Table 20: FMC C connector clock signal input

FMC C VCC/VCCIO:

Table 21: FMC C connector available VCC/VCCIO

FMC C Cooling Fan:

Table 22: FMC C connector cooling fan

FMC D

FMC D Interfaces:

Table 23: FMC D connector interfaces

FMC D MGT Lanes:

Table 24: FMC D connector MGT lanes

FMC D Clock Signals:

Table 25: FMC D connector clock signal input

FMC D VCC/VCCIO:

Table 26: FMC D connector available VCC/VCCIO

FMC D Cooling Fan:

Table 27: FMC D connector cooling fan

FMC E

FMC E Interfaces:

Table 28: FMC E connector interfaces

FMC E MGT Lanes:

Table 29: FMC E connector MGT lanes

FMC E Clock Signals:

Table 30: FMC E connector clock signal input

FMC E VCC/VCCIO:

Table 31: FMC E connector available VCC/VCCIO

FMC E Cooling Fan:

Table 32: FMC E connector cooling fan

XMOD JTAG Interface

JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35.

Figure X: XMOD header J24 and J35

Signal Assignment of XMOD header J24 and J35

Table 33: XMOD interface signals

The JTAG interfaces of the TEB0911 UltraRack board can accessed with the XMOD-FT2232H adapter-board TE0790. The on-board devices Zynq MPSoC U1 and SC CPLD U27 can be programmed via USB2.0 interface of the TE0790 board.

XMOD-Header J24 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U27.

XMOD-Header J35 is designated to program the System Controller CPLD U27 via USB interface, the 4 GPIO/UART pins (XMOD1_A/B/E/G) of this header are also routed to the System Controller CPLD U27.
To program the System Controller CPLD, the JTAG interface of this devices have to be activated by DIP-switch S3-2.

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:

Table 34: XMOD adapter board DIP-switch positions for voltage configuration

Gigabit Ethernet Interface

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 502. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the System Controller CPLD bank 2, pins Y12, Y13 and Y14.

Figure X: Gigabit Ethernet Interface

Table 35: Ethernet PHY interface connections

USB3 Interface

On the TEB0911 board two USB3 Superspeed ports are available to the user, which are downward compatible to USB2 Highspeed.

Figure X: USB3 Interface

The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

Table 36: USB3 signals and interfaces

SFP+ Interface

The TEB0911 board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) with data transmission rates up to 10 Gbit/s.

Block diagram below shows the dependencies between the implied devices which establish the SFP+ interface:

Figure X: SFP+ Interface

Table 37: SFP+ signals and interfaces

SSD Interface

On the TEB0911 UltraRack board one SSD interface is available provided by a NGFF (Next Generation Form Faktor) M.2 socket (Key M) which supports data transmission rates for PCIe3, SATA3 and USB3 interfaces.

Figure X: SSD Interface

Table 38: SSD signals and interfaces

DisplayPort Interface

DDR4 Memory Socket

CAN Interface

SD Card Interface

Describe SD Card interface  shortly here if the module has one...

Table x: SD Card interface signals and connections.

4-Wire PWM FAN Connectors

PLL Clock Interfaces

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On-board Peripherals

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

The TEB0911 UltraRack is equipped with one System Controller CPLDs - Lattice Semiconductor LCMXO2-7000HC (MachXO2 Product Family) with the schematic designators U27.

The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic of the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank differential lanes and I²C interface.

The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS (MIO), PL bank pins and I²C interface.

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Table x: System Controller CPLD I/O pins.

High-speed USB ULPI PHY

USB PHY (U9) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U10).

Table 17: USB PHY interface connections

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

4-port USB3.0 Hub

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.

On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.

The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.

Table 18: Ethernet PHY interface connections

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

8-Channel I²C Switches

All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.

For this purpose, the TEB0911 carrier board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.

Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.

The I²C bus works internally on-module with reference voltage 1.8V, it is connected to the MPSoC I²C interface via PS MIO bank (pins MIO38, MIO39) configured as master.

Table 19: MIO-pin assignment of the module's I²C interface

I²C addresses for on-board slave devices are listed in the table below:

Table 20:  On-board peripherals' I²C-interfaces device slave addresses

Configuration EEPROMs

The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:

Table 21:  On-board configuration EEPROMs overview

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.

eMMC Memory

The TEB0911 UltraRack board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

Oscillators

The TEB0911 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

Table 16: Reference clock signal oscillators

Programmable Clock Generator Si5338A

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

 Table : Programmable quad PLL clock generator inputs and outputs.

Programmable Clock Generator Si5345A

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table : Reference clock signals.

On-board LEDs

Table : On-board LEDs.

User Buttons

Configuration DIP-switches

Backup Battery Holder

Power and Power-On Sequence

Power Consumption

The maximum power consumption of the board mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table : Typical power consumption, *to Be Determined soon with reference design setup.

Power supply with minimum current capability of ?? A for system startup is recommended.

The TEB0911 UltraRack board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular on-board DC-DC converters.

The Processing System contains three Power Domains:

• Battery Power Domain (BBRAM and RTC)
• Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
• Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)
• Programmable Logic (PL)

Power Distribution Dependencies

There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

Power-On Sequence

The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller CPLD U27:

1. Low-Power Domain (LPD)
2. Programmable Logic (PL) and Full-Power Domain (FPD)
3. GTH, PS GTR transceiver and DDR memory

Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance is asserted.

Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.

Figure : Module power-on diagram.

Voltage Monitor Circuit

If the module has one, describe it here...

Power Rails

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Table : Module power rails.

Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.

Bank Voltages

Table : Module PL I/O bank voltages.

Board to Board Connectors

Variants Currently In Production

NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.

Table : Module variants.

Technical Specifications

Absolute Maximum Ratings

Table : Module absolute maximum ratings.

Recommended Operating Conditions

Table : Module recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: ... mm × ... mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: ... mm.

• PCB thickness: ... mm.

• Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Put mechanical drawings here...

Figure : Module physical dimensions drawing.

Revision History

Hardware Revision History

Table : Module hardware revision history.

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Put picture of actual PCB showing model and hardware revision number here...

Figure : Module hardware revision number.

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy241.$Proxy3496#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]		John Hartfiel	Remove Link to Download
2017-11-10	v.58	Ali Naseri	PDF-Link to online version of the TRM fixed Online Link of download area fixed
2017-09-06	v.56	Jan Kumann	Template revision 1.64 SD Card interface added.
2017-09-02	v.54	Jan Kumann	DDR Memory section added.
2017-08-27	v.43	John Hartfiel	New template revision 1.6. Moved Boot Process between Overview and Signals, Interfaces and Pins section.
2017-08-16	v.42	Jan Kumann	New template revision 1.5 MGT Lanes section changed. Programmable PLL Clock section changed. "Figure" and "Table" labels added. Module variants and temperatures ranges sections improved. Comments added/changed, also formatted as italic now.
2017-08-07	v.32	Jan Kumann	Few corrections and cosmetic changes.
2017-07-14	v.25	John Hartfiel	Removed weight section update template version
2017-06-08	v.20	John Hartfiel	Add revision number and update document change history
2017-05-30	v.1	Jan Kumann	Initial document.
	all	Jan Kumann, John Hartfiel

Table : Document change history.

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