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Table of contents

Overview

TEF0008 design for MAX10 FPGA U2:  10M08SAU169C8G.

Feature Summary

  • SFP Control
  • I2C MUX
  • level shifter
  • LED Control

Firmware Revision and supported PCB Revision

See Document Change History.

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
PLL_SDA_ioBidirK2I2C Si5345A-B
PLL_SCL_oOutK1I2C Si5345A-B
LEDOutC2Status LED
A_LOS_iInH9SFP A Signal Loss (HIGH indicates signal loss)

A_MDEF0_i

InG9SFP A Modul Absent (HIGH when module physically absent)
A_RS0_oOutJ9SFP A Rate Select RX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)
A_RS1_oOutH8SFP A Rate Select TX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)
A_SCL_oOutK10SFP A I2C Clock 
A_SDA_ioBidirK11SFP A I2C Data

A_TX_DIS_o

OutH10SFP A (HIGH disables transmitter)
A_TX_FAULT_iInL12SFP A Laser fault (HIGH indicates fault)
B_LOS_iInK12SFP B Signal Loss (HIGH indicates signal loss)
B_MDEF0_iInJ13SFP B Modul Absent (HIGH when module physically absent)
B_RS0_oOutJ12SFP B Rate Select RX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)
B_RS1_oOutL13SFP B Rate Select TX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)
B_SCL_oOutH13SFP B I2C Clock
B_SDA_ioBidir

G10

SFP B I2C Data
B_TX_DIS_oOutG13SFP B (HIGH disables transmitter)

B_TX_FAULT_i

InG12SFP B Laser fault (HIGH indicates fault)

C_LOS_i

In

F12

SFP C Signal Loss (HIGH indicates signal loss)
C_MDEF0_iInE12SFP C Modul Absent (HIGH when module physically absent)
C_RS0_oOutF13SFP C Rate Select RX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)
C_RS1_oOutF9SFP C Rate Select TX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)
C_SCL_oOutE13SFP C I2C Clock
C_SDA_ioBidirD11SFP C I2C Data
C_TX_DIS_oOutD12SFP C (HIGH disables transmitter)
C_TX_FAULT_iInC12SFP C Laser fault (HIGH indicates fault)
D_LOS_iInB11SFP D Signal Loss (HIGH indicates signal loss)

D_MDEF0_i

InB12SFP D Modul Absent (HIGH when module physically absent)
D_RS0_oOutB13SFP D Rate Select RX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)
D_RS1_oOutC13SFP D Rate Select TX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)
D_SCL_oOutA12SFP D I2C Clock
D_SDA_ioBidirF10SFP D I2C Data
D_TX_DIS_oOutE9SFP D (HIGH disables transmitter)

D_TX_FAULT_i

InD9SFP D Laser fault (HIGH indicates fault)
LA00_PInM9SCL In
LA00_NInN5SDA In
LA01_POutL4SDA Out
LA01_NInJ5I2C GPIO MUX 0

LA02_P

InM13I2C GPIO MUX 1

LA02_N

InM12I2C GPIO MUX 2
LA03_NInN6RS0
LA03_PInM5TX_DISABLE
LA04_NOutK7TX Fault A+B+C+D
LA04_PInJ7RS1

LA05_N

OutL5LOS A
LA05_POutK5DEF0 A, SFP A Inserted Flag
LA06_NOutJ6LOS B
LA06_POutK6DEF0 B, SFP B Inserted Flag
LA07_NOutM8LOS C
LA07_POutN8DEF0 C, SFP C Inserted Flag
LA08_NOutM7LOS D
LA08_POutN7DEF0 D, SFP D Inserted Flag
LA09_P  -N4/currently unused
LA09_N -

M4

/currently unused


Functional Description

SFP Control

  • Input Signal LA03_N sets all four SFP RX modes (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)1
  • Input Signal LA04_P sets all four SFP TX modes (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)1
  • Output Signals LA05_N, LA06_N, LA07_N and LA08_N indicate signal loss of SFP A, B, C and D respectively (HIGH indicates signal loss).
  • Output Signals LA05_P, LA06_P, LA07_P and LA08_P indicate SFP A, B, C and D module absend (HIGH when module physically absent).
  • Output Signal LA04_N  is HIGH when at least one of the four SFPs indicate Laser fault.
  • Input LA03_P HIGH sets for all SFPs where the module is physically available (MDEF0_i is LOW) the TX_DIS signal to LOW.2

1SFP Control and I2C register writes of RX/TX modes are couppled with a logical or. If at least one of them indicates HIGH the 10GBASE-SR is activated.

2Inverted control as we can not enable weak pulldown in MAX10, we use weak pullup. TX are all ENABLED at default power up, so the card is working with no FMC LA pin driven.

I2C

  • LA00_P, LA00_N and LA01_P form a "three wire I2C" bus with seperate data in and output.
  • LA01_N, LA02_P and LA02_N are used Selector for the MUX.


SEL
I2C device
000SFP A
001SFP B
010SFP C
011SFP D
100Si5345 Clock Generator

For I2C adresses see TEF0008 TRM.

LED

LED is used as Status LED and is on if at least on SFP is connected.

JTAG

MAX10 JTAG for programming is always enabled and accessable via the FMC connector, pin header J3 and testpoints.

Appx. A: Change History and Legal Notices

Revision Changes

Initial revision.

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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REV01REV01

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  • small style update
2018-06-07v.01REV01REV01Martin Rohrmüller
  • initial document

All

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Appx. A: Legal Notices

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