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Table of Contents
Overview
The Trenz Electronic TEC0850 board is an industrial-grade CompactPCI card (3U form factor) integrating a Xilinx Zynq UltraScale+ MPSoC, one DDR4 SDRAM SODIMM socket with 64bit wide databus, max. dual 512 MByte Flash memory for configuration and operation, 24 Gigabit transceivers on PL side and 4 on PS side, powerful switch-mode power supplies for all on-board voltages, USB2 and USB3 FIFO bridges and a large number of configurable I/Os available on the CompactPCI backplane connectors.
Key Features
Zynq UltraScale+ MPSoC ZU15
- Front side interface connectors
- RJ-45 GbE Ethernet interface
- Elbow Socket with 4x on-board 8bit DAC output
- MicroSD Card connector
- USB2 and USB3 to FIFO bridge connector
- 4x status LEDs
- 4 CompactPCI slots for backplane connection (3U form factor)
- 24 GTH lanes
- 4 PS GTR lanes
- USB2 interface
- 64 Zynq PL HP I/O's
- 8x PLL clock input
- JTAG, I²C and 7 user I/O's to MAX10 FPGA
64bit DDR4 SODIMM (PS connected), 8 GByte maximum
Dual parallel QSPI Flash (bootable), 512 MByte maximum
- 26-pin header with 20 Zynq PL HD I/O's
- 3-pin header with 2 MAX10 FPGA I/O's
- System Controller (Altera MAX10 FPGA SoC)
- Power Sequencing
- System management and control for MPSoC and on-board peripherals
- Si5345 programmable 10 output PLL clock generator
- Quad and Dual PLL clock generators
- 2x 4bit DIP switches
- 1x user push button
- Zynq MPSoC cooling FAN connector
- On-board high-efficiency DC-DC converters
Block Diagram
Figure 1: TEC0850-02 block diagram
Main Components
Figure 2: TEC0850-02 main components
- GbE RJ-45 MagJack, J7
- DAC output 5-pin elbow receptacle socket, J15
- Micro USB2 B receptacle connector, J9
- MicroSD Card socket, J11
- USB C connector, J10
- LED light pipes J14 integrating LEDs D1 ... D4
- 4bit DIP-switch, S2
- 4bit DIP-switch, S1
- FTDI FT2232 USB2 to FIFO bridge, U4
- 3-pin header, J8
- MAX10 FPGA JTAG/UART 10-pin header, J13
- Altera MAX10 FPGA System Controller, U18
- 4-Wire PWM fan connector, J17
- Zynq MPSoC PL I/O 26-pin header, J16
- DDR4 SO-DIMM 260-pin socket, U3
- Battery Holder CR1220, B1
- 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U24
- 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U25
- DC-DC Converter LT8471IFE @+5VA/-5VA, U74
- DC-DC Converter EM2130L02QI @VCCINT_0V85, U17
- DC-DC Converter 171050601 @5V, U50
- Xilinx Zynq Ultrascale+ MPSoC, U1
- Si5345A 10-output I²C programmable PLL clock, U14
- Main power fuse @2.5A/16V, F1
- cPCI slot, J1
- cPCI slot, J4
- cPCI slot, J5
- cPCI slot, J6
- FTDI FT601Q USB3 to FIFO bridge, U9
- TI THS5641 8bit DAC ,U28
- TI THS5641 8bit DAC ,U31
- TI THS5641 8bit DAC ,U29
- TI THS5641 8bit DAC ,U33
- Marvell Alaska 88E1512 GbE PHY ,U20
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
.. | .. | .. |
| OTP Flash area | Empty | Not programmed. |
Table 1: Initial delivery state of programmable devices on the module.
Control Signals
Signals, Interfaces and Pins
Subsections...
Figure 2: TEC0850-02 Overview IO interfaces
USB-C
Front panel USB-C Interface connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.
| FT601Q Signal | FPGA Pin |
|---|---|
| FIFO_CLK | |
| ... |
Table x: FTDI Signals
See FT600Q-FT601Q IC Datasheet for interface details.
MicroUSB
Front panel Micro-USB Interface provides access to UART and JTAG functions via FTDI FT2232 chip. Use of this feature requires that USB driver is installed on your host PC. UART0 with MIO 22 .. 23 should be selected in "Zynq UltraScale+ MPSoC" configuration.
The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.
Figure 3: JTAG/UART Interface
SD
There are some limitations to use SD card Interface in Linux.
- Zynq UltraScale+ SD controller is working only in the 3.3V mode as it connected to SD card socket using 1.8V to 3.3V level shifter U10.
- Micro SD card socket has no "Write Protect" switch.
To force Linux driver not to use this features add following instructions to device tree file.
&sdhci1 {
no-1-8-v;
disable-wp;
};
RJ45 - Ethernet
cPCIe
...
MGT
The TEC0850 board has 30 MGT lines routed to backplane connectors.
| Bank | Connector | Lanes |
|---|---|---|
| PL 128 | J4G and J4H | 4 |
| PL 129 | J5A and J5B | 4 |
| PL 130 | J5C and J5D | 4 |
| PL 230 | J4G and J4H | 4 |
| PL 229 | J5A and J5B | 4 |
| PL 228 | J5C and J5D | 4 |
| PS 505 | J1A | 4 |
Table x: MGT Banks
MGT reference clocks are connected to banks 129, 229 and 505. Banks 128 and 130 should share clock from bank 129, banks 230 and 228 from bank 229.
USB Interface
Zynq UltraScale+ USB controller connected to backplane connector J1C via USB PHY chip U11.
DDR4 SODIMM Socket
The Zynq UltraScale+ DDRC hard memory controller is wired to the DDR4 SODIMM Socket U3.
Circular Push Pull Connector
PicoBlade Connector
Pin Heater 2,54mm (2x5)
Battery holder
On-board Peripherals
Subsections...
Zynq UltraScale XCZU15EG MPSoC
The TEC0850 board is populated with the Zynq UltraScale+ XCZU15EG-1FFVB1156E MPSoC.
Main IO interfaces are shown on the image below.
PS MIO Configuration
| MIO | Interface |
|---|---|
| MIO 0...12 | QSPI Flash Memory |
| MIO 20...21 | I2C 1 |
| MIO 22...23 | UART 0 |
| MIO 26...37 | GEM 0 |
| MIO 46...51 | SD 1 |
| MIO 52...63 | USB 0 |
| MIO 64...75 | USB 1 |
| MIO 76...77 | MDIO 0 |
Table x: Default MIO Configuration
MAX10 System Controller
System controller chip is Intel MAX10 10M08SAU169C8G Chip with board control firmware.
Programmable Clock Generators
Figure 2: TEF1001-02 main components
I2C
The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.
| I2C address | Chip | Description |
|---|---|---|
| 0x69 | U14 Si5345 | Clock generator and distributor |
Table x: SI5345 I2C address
Oscillators
FTDIs
FT2232H
FT601Q-B-T
Quad-SPI Flash Memory
Board has two N25Q512A11G1240E connected in a dual parallel mode.
EEPROMs
I2C
The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.
| I2C address | Chip | Description |
|---|---|---|
| 0x50 | U63 24AA128T-I/ST | 128K Serial EEPROM |
| 0x53 | U64 24AA025E48T-I/OT | 2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity |
Table x: EEPROMs I2C Addresses
USB PHY
Gigabit Ethernet PHY
Board has Marvell Alaska 88E1512 Ethernet PHY which use MDIO address 1.
8Bit DACs
Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.
DIP-Switches
S1
| Switch | Description |
|---|---|
| 1 | Boot Mode 0 |
| 2 | Boot Mode 1 |
| 3 | Boot Mode 2 |
| 4 | Boot Mode 3 |
Table x: LEDs
See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes are
| Boot Mode | SW1:4 | SW1:3 | SW1:2 | SW1:1 |
|---|---|---|---|---|
| JTAG Boot Mode | ON | ON | ON | ON |
| Quad-SPI | ON | ON | ON | OFF |
| SD Card | ON | ON | OFF | OFF |
Table x: Recommended Boot Modes
S2
| Switch | Description |
|---|---|
| 1 | SC JTAGEN |
| 2 | EEPROM WP (Write protect) |
| 3 | FPGA PUDC |
| 4 | SC Switch (Reserved for future use) |
Table x: S2 DIP Switch
Buttons
LEDs
| LED | Signal | Chip | Pin | Description |
|---|---|---|---|---|
| Front panel LED 1 (Red) | LED_FP_1 | FPGA U1 | AF15 | PL User defined LED |
| Front panel LED 2 (Green) | LED_FP_2 | FPGA U1 | AG15 | PL User defined LED |
| Front panel LED 3 (Green) | LED_FP_3 | FPGA U1 | AE15 | PL User defined LED |
| Front panel LED 4 (Green) | LED_FP_4 | SC U18 | M4 | Power Good |
Table x: LEDs
Power and Power-On Sequence
Power Consumption
The maximum power consumption of a module mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
| Power Input | Typical Current |
|---|---|
| TBD* |
Table x: Typical power consumption.
Power Distribution Dependencies
Figure 3: Power Distribution
Power-On Sequence
Figure 4: Power-On Sequence Diagram
Voltage Monitor Circuit
Power Rails
Bank Voltages
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Unit | Notes / Reference Document |
|---|---|---|---|---|
| LP_DCDC | -0.3 | 4 | V | TPS3106K33DBVR data sheet |
| GT_DCDC | -0.3 | 7 | V | TPS82085SIL data sheet |
| PS_BATT | -0.5 | 2 | V | Xilinx DS925 data sheet |
| PLL_3V3 | -0.5 | 3.8 | V | Si5345/44/42 data sheet |
| VCCO for HD I/O banks | -0.5 | 3.4 | V | Xilinx DS925 data sheet |
| VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet |
| I/O input voltage for HD I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
| I/O input voltage for HP I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
| PS I/O input voltage (MIO pins) | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
| PS GTR reference clocks absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 |
| PS GTR absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 |
| MGT clock absolute input voltage | -0.5 | 1.3 | V | Xilinx document DS925 |
MGT Receiver (RXP/RXN) and transmitter | -0.5 | 1.2 | V | Xilinx DS925 data sheet |
Voltage on input pins of | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, see schematic for VCC |
Voltage on input pins (nMR) of | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, |
| "Enable"-signals on TPS82085SIL (EN_PLL_PWR, EN_LPD) | -0.3 | 7 | V | TPS82085SIL data sheet |
Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
Table x: Module absolute maximum ratings.
Recommended Operating Conditions
| Parameter | Min | Max | Unit | Notes / Reference Document |
|---|---|---|---|---|
| PL_DCIN | 3.3 | 6 | V | EN63A0QI / TPS82085SIL data sheet |
| DCDCIN | 3.3 | 6 | V | TPS82085SIL / TPS51206PSQ data sheet |
| LP_DCDC | 3.3 | 3.6 | V | TPS82085SIL / TPS3106 data sheet |
| GT_DCDC | 3.3 | 6 | V | TPS82085SIL data sheet |
| PS_BATT | 1.2 | 1.5 | V | Xilinx DS925 data sheet |
| PLL_3V3 | 3.3 | 3.47 | V | Si5345/44/42 data sheet 3.3V typical |
| VCCO for HD I/O banks | 1.14 | 3.4 | V | Xilinx DS925 data sheet |
| VCCO for HP I/O banks | 0.95 | 1.9 | V | Xilinx DS925 data sheet |
| I/O input voltage for HD I/O banks. | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
| I/O input voltage for HP I/O banks | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
| PS I/O input voltage (MIO pins) | -0.2 | VCCO_PSIO + 0.2 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
| PL bank reference voltage VREF pin | -0.5 | 2 | V | Xilinx DS925 data sheet |
| Voltage on input pins of NC7S08P5X 2-Input AND Gate | 0 | VCC | V | NC7S08P5X data sheet, |
Voltage on input pin 'MR' of | 0 | VDD | V | TPS3106 data sheet, |
Table x: Module absolute maximum ratings.
Physical Dimensions
Create DrawIO object here: Attention if you copy from other page, use
Figure x: Physical dimensions drawing
Variants Currently In Production
| Trenz shop TE0xxx overview page | |
|---|---|
| English page | German page |
Table x: Shop Overview
Revision History
Hardware Revision History
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| - | 01 | Prototypes | ||
Table x: Module absolute maximum ratings.
Document Change History
| Date | Revision | Contributor | Description |
|---|---|---|---|
| |||
| -- | all | -- |
Table x: Document change history.
Disclaimer
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
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Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
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Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
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