Table of contents
Overview
TEC0850 design for MAX10 FPGA U18: 10M08SAU169C8G.
Feature Summary
- SC to HD-IO Bank Interface
Firmware Revision and supported PCB Revision
See Document Change History.
Product Specification
Port Description
Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
---|---|---|---|---|
FTDI_RXD | in | UART receive data from FTDI | ||
FTDI_TXD | out | UART transmit data to FTDI | ||
MIO22 | out | UART receive data to FPGA | ||
MIO23 | in | UART receive data from FPGA | ||
ZYNQ_TDO | in | FPGA JTAG TDO | ||
ZYNQ_TCK | out | FPGA JTAG TCK | ||
ZYNQ_TDI | out | FPGA JTAG TDI | ||
ZYNQ_TMS | out | FPGA JTAG TMS | ||
ADBUS0 | in | FTDI JTAG TCK | ||
ADBUS1 | in | FTDI JTAG TDI | ||
ADBUS2 | out | FTDI JTAG TDO | ||
ADBUS3 | in | FTDI JTAG TMS | ||
USB_BTN | in | Front panel button | ||
LED4 | out | Front panel LED4 | ||
MR | out | Supervisor Reset output | ||
SRST_B | out | FPGA SRST_B | ||
FTDI_RST | out | FPGA RST_B | ||
PLL_RST | out | Clock chip Reset | ||
EN_DAC1 | out | DAC1 Power Enable | ||
EN_DAC2 | out | DAC2 Power Enable | ||
EN_DAC3 | out | DAC3 Power Enable | ||
EN_DAC4 | out | DAC4 Power Enable | ||
EN_FPD | out | FPD Power Enable | ||
EN_LPD | out | LPD Power Enable | ||
EN_DDR | out | DDR Power Enable | ||
EN_PSGT | out | PSGT Power Enable | ||
ON_GT_L | out | GT_L Power Enable | ||
ON_GT_R | out | GT_R Power Enable | ||
PG_PSGT | in | PSGT Power Good | ||
LP_GOOD | in | LP Power Good | ||
PG_GT_L | in | GT_L Power Good | ||
PG_GT_R | in | GT_R Power Good | ||
PG_PL | in | PL Power Good | ||
PG_DDR | in | DDR Power Good | ||
F1PWM | out | FAN PWM Control | ||
F1SENSE | in | FAN Sense | ||
DONE | in | FPGA DONE | ||
IO1 | in | FPGA I2C SCL_t | ||
IO2 | out | FPGA I2C SCL_i | ||
IO3 | in | FPGA I2C SDA_t | ||
IO4 | out | FPGA I2C SDA_i | ||
IO5 | in | FPGA User LED control | ||
SCL_R | out | SCL Strong Pull-Up Enable | ||
SDA_R | out | SDA Strong Pull-Up Enable | ||
SCL | inout | I2C SCL | ||
SDA | inout | I2C SDA |
Functional Description
SC to HD-IO Bank Interface
SC I/O # | Function | FPGA IO | |
IO1 | SCL OUT | G18 | |
IO2 | SCL IN | G19 | |
IO3 | SDA OUT | K18 | |
IO4 | SDA IN | H19 | |
IO5 | User LED | J17 | Drive SC LED, if configured in "Control Register" |
IO6 | - | H17 | |
IO7 | - | H18 | |
IO8 | - | L18 | |
IO9 | - | L17 | |
IO10 | - | K17 |
Appx. A: Change History and Legal Notices
Revision Changes
Initial revision.
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
---|---|---|---|---|---|
REV02 | REV02 |
| |||
All |
Appx. A: Legal Notices
Overview
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