Table of contents
Overview
TEC0850 design for MAX10 FPGA U18: 10M08SAU169C8G.
Feature Summary
- SC to HD-IO Bank Interface
- I²C Backplane interface
- I²C System Control interface
- Power control
- Power status
- FAN Control
- FAN Status
- Power status indication
Firmware Revision and supported PCB Revision
See Document Change History.
Product Specification
Port Description
| Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
|---|---|---|---|---|
| FTDI_RXD | in | UART receive data from FTDI | ||
| FTDI_TXD | out | UART transmit data to FTDI | ||
| MIO22 | out | UART receive data to FPGA | ||
| MIO23 | in | UART receive data from FPGA | ||
| ZYNQ_TDO | in | FPGA JTAG TDO | ||
| ZYNQ_TCK | out | FPGA JTAG TCK | ||
| ZYNQ_TDI | out | FPGA JTAG TDI | ||
| ZYNQ_TMS | out | FPGA JTAG TMS | ||
| ADBUS0 | in | FTDI JTAG TCK | ||
| ADBUS1 | in | FTDI JTAG TDI | ||
| ADBUS2 | out | FTDI JTAG TDO | ||
| ADBUS3 | in | FTDI JTAG TMS | ||
| USB_BTN | in | Front panel button | ||
| LED4 | out | Front panel LED4 | ||
| MR | out | Supervisor Reset output | ||
| SRST_B | out | FPGA SRST_B | ||
| FTDI_RST | out | FPGA RST_B | ||
| PLL_RST | out | Clock chip Reset | ||
| EN_DAC1 | out | DAC1 Power Enable | ||
| EN_DAC2 | out | DAC2 Power Enable | ||
| EN_DAC3 | out | DAC3 Power Enable | ||
| EN_DAC4 | out | DAC4 Power Enable | ||
| EN_FPD | out | FPD Power Enable | ||
| EN_LPD | out | LPD Power Enable | ||
| EN_DDR | out | DDR Power Enable | ||
| EN_PSGT | out | PSGT Power Enable | ||
| ON_GT_L | out | GT_L Power Enable | ||
| ON_GT_R | out | GT_R Power Enable | ||
| PG_PSGT | in | PSGT Power Good | ||
| LP_GOOD | in | LP Power Good | ||
| PG_GT_L | in | GT_L Power Good | ||
| PG_GT_R | in | GT_R Power Good | ||
| PG_PL | in | PL Power Good | ||
| PG_DDR | in | DDR Power Good | ||
| F1PWM | out | FAN PWM Control | ||
| F1SENSE | in | FAN Sense | ||
| DONE | in | FPGA DONE | ||
| IO1 | in | FPGA I2C SCL_t | ||
| IO2 | out | FPGA I2C SCL_i | ||
| IO3 | in | FPGA I2C SDA_t | ||
| IO4 | out | FPGA I2C SDA_i | ||
| IO5 | in | FPGA User LED control | ||
| SCL_R | out | SCL Strong Pull-Up Enable | ||
| SDA_R | out | SDA Strong Pull-Up Enable | ||
| SCL | inout | I2C SCL | ||
| SDA | inout | I2C SDA |
Functional Description
SC to HD-IO Bank Interface
| SC I/O # | Function | FPGA IO | |
| IO1 | SCL OUT | G18 | |
| IO2 | SCL IN | G19 | |
| IO3 | SDA OUT | K18 | |
| IO4 | SDA IN | H19 | |
| IO5 | User LED | J17 | Drive SC LED, if configured in "Control Register" |
| IO6 | - | H17 | |
| IO7 | - | H18 | |
| IO8 | - | L18 | |
| IO9 | - | L17 | |
| IO10 | - | K17 |
I²C Interface
To use SC I²C interface corresponding connection should be configured in the FPGA project. There are 2 standard I²C interface controllers, which can be used AXI_IIC or Zynq UltraScale+ MPSoC integrated I²C controller.
AXI_IIC
Zynq UltraScale+ MPSoC integrated I²C controller
With this configuration, I²C device with address 0x20 should be visible on I²C bus
This device is an emulation of TCA6416 I²C GPIO Chip. GPIO input and output pins are used to get status and control the system.
| Address | Register | Description |
|---|---|---|
| 0 | Input Port 0 | Power status register: Bit 0 - LP_PGOOD Bit 1 - PG_PL Bit 2 - PG_PSGT Bit 3 - PG_GT_L Bit 4 - PG_GT_R Bit 5 - PG_DDR Bit 6 - Not Used "0" Bit 7 - Not Used "0" |
| 1 | Input Port 1 | FAN Status register Bits 7:0 - FAN RPM/1000 (Nominal Sepa HFB44B-12A speed is 8000 RPM) |
| 2 | Output Port 0 | Control register 0 Bits 1:0 - LED Control (Default "01") Bit 2 - SMB Strong Pull-Up Enable (Default "1") Bit 3 - Enable DAC1 Power (Default "1") Bit 4 - Enable DAC2 Power (Default "1") Bit 5 - Enable DAC3 Power (Default "1") Bit 6 - Enable DAC4 Power (Default "1") Bit 7 - Enable FPD Power (Default "1") |
| 3 | Output Port 1 | Control register 1 Bit 0 - Enable LPD Power (Default "1") Bit 1 - Enable DDR Power (Default "1") Bit 2 - Enable PSGT Power (Default "1") Bit 3 - Enable GT_L Power (Default "1") Bit 4 - Enable GT_R Power (Default "1") Bit 5 - Enable FAN Power (Default "1") (Works only if 4-wire FAN is used) Bit 6 - Not used Bit 7 - Not used |
I²C GPIO registers can be operated with directly, using Linux i2cset and i2cget commands
root@petalinux:~# # Disable LED4 root@petalinux:~# i2cset -y 0 0x20 2 0xFC root@petalinux:~# # Get Power status root@petalinux:~# i2cget -y 0 0x20 0 b 0x3f root@petalinux:~# # Get FAN RPM/1000 root@petalinux:~# i2cget -y 0 0x20 1 b 0x08
or I²C GPIO device driver can be instantiate in Linux device tree (project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi).
&i2c0 {
tca6416: tca6416@21 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
Appx. A: Change History and Legal Notices
Revision Changes
RE02 to REV03
- Add I²C GPIO core
- FAN Control/FAN Status
- Power control
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
|---|---|---|---|---|---|
| REV03 | REV02 |
| |||
| 2018-08-15 | v.3 | REV02 | REV02 | Antti Lukats |
|
| All |
Appx. A: Legal Notices
Overview
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