Achtung beim Schritt HDL generate
Was macht das TCL-Script mit den Pins/? ?
Optionen im Plattformdesigner, die sinnvoll wären eingestellt zu werden:
USB Controllers
SPI Controllers
Enable MPU Interrupts auswählen, dann muss das verbunden werden oder Exportiert, wohin / womit?
Setup of your own project
The project wizard of Quartus lite guides through the setup of a project.
Before using it, it is suggested to create a project directory for storing it via a file browser.
Quartus lite does not create a folder for you. The generation of the bootloaders requires a
SoC EDS Shell with root privileges on a windows systems. Their file system access
is limited to the C drive. Therefore it is best practice for Windows users to store the project
on the C drive.
In essence, the project setup consists pointing to the project directory, naming the project,
and adding a device to it.
This guide uses the folder Project and the project itself is named HPSexample.
The steps in detail:
File → New Project Wizard ... Setup the path to the project directory and name the project, click next.
In the following windows - Project Type - and - Add Files - is nothing further required other
than clicking Next.
In the next window - Family, Device & Board Settings - it is required to select either a
FPGA Device or a Board from the List.
Copy 5CSEMA5F31C8(N) into the field Name filter , this reduces the Device list, and select it in the list.
In the window EDA Tool Settings just click Next and Finish in the following window - Summary.
Quartus places the folder db, two files HPSexample.qpf and HPSexample.qsf into the project folder
and the setup is accomplished.
Plattform Designer
This program generates the files needed to connect and configures the HPS so that it gets connected to the physical board resources.
The basic storage resources the HPS needs are System Memory and SD card access, to communicate the basic interfaces are Uart and i²c.
These files are:
- HPSexample.sopinfo - describes all of the components and connections in your system and
parameterization of each component in the system
- PlattformEditorHPS.qip - The contains paths for all of the files for an IP core
- (hps_isw_)handoff folder - Folder containing general and SoC / board specific source files for generating the bootloaders
The Plattform Designer can be opened via Tools → Plattform Designer and later on, the output must be added into
project. Instead, both steps can be performed through adding a Qsys System File to the project.
File → New , select Qsys System File and press OK, the Plattform Designer opens in a new window.
To configure the resources and interfaces of the HPS, it needs first to be added into the system,
Type into the search field in the upper left column hps.
Select Arria V/Cyclone V Hard Processor System via double click from the tree:
Library - Processors and Peripherals - Hard Processor Systems - Arria V/Cyclone V Hard Processor System
The window - Arria V/Cyclone V Hard Processor System - hps_0 - opens. To setup the peripheral of the HPS ,
transfer everything of the following list into the tabs mentioned. Everything not mentioned must be left untouched.
Tab FPGA Interface:
Uncheck Enable MPU standby and event signals (default)
AXI Bridges
FPGA-to-HPS interface width: unused
HPS-to-FPGA interface width: unused
Lightweight HPS-to-FPGA interface width: unused
Tab Peripheral Pins:
Quad SPI Flash Controller - QSPI pin: HPS I/O Set 0
SD/MMC Controller - SDIO pin: HPS I/O Set 0 - SDIO mode: 4-bit Data
UART Controllers - UART0 pin: HPS I/O Set 0 - UART0 mode: no Flow Control
I2C Controllers - I2C0 pin: HPS I/O Set 1 - I2C1 pin: HPS I/O Set 0
Tab HPS Clocks:
As is / Accept the default values (for both subtabs)
Tab SDRAM - Subtask Phy Settings:
Memory clock frequency: 333.3 MHz
PLL reference clock frequency: 25 MHz
Tab SDRAM - Subtask - Memory Parameters:
Memory device speed grade: 800.0 MHz
Total interface width: 32
Row Address width: 16
Column Address width: 10
Memory Initialization Options
Memory CAS latency setting: 5
ODT Rtt nominal value: RZQ/6
Memory write CAS latency settings: 5
Tab SDRAM - Subtask - Memory Timing:
tIS (base): 180 ps tIH (base): 140 ps tDS (base) 30 ps tDH (base): 65 ps tDQSQ: 100 ps tQH 0.38 cycles tDQSCK_ 225 ps
tDQSS: 0.27 cycles tQSH: 0.4 cycles tDSH:0.18 cycles tDSS: 0.18 cycles tINIT: 500 us tMRD (tMRW): 4 cycles
tRAS: 35.0 ns tRCD: 13.75 ns tRP: 13.75 ns tREFI (tREFIab): 7.8 us tRFC (tRFCab): 350.0 ns tWR: 15.0 ns
tWTR: 4 cycles tFAW: 40 ns tRRD: 12.0 ns tRTP: 12.0 n
Tab SDRAM - Subtask - Board Settings:
Board Skews
Maximum CK delay to DIMM/device: 0.03
Maximum DQA delay to DIMM/device: 0.02
Minimum delay between CK and DQS: 0.09
Maximum delay between CK and DQS: 0.16
Maximum skew within DQS group: 0.01
Maximum skew between DQS groups: 0.08
Maximum skew within address and command bus: 0.03
Click Finish in the bottom left to close the window - Arria V/Cyclone V Hard Processor System - hps_0 .
To change or correct these parameters later, (double) click onto the IP cores top entry in the tab System Contents.
Add Connections via clicking into the circle marked with a red rectangle in th picture above.
hps_0 - h2f_reset → clk_0 - clk_in_reset
clk_0 - clk → hps_0 - f2h_sdram0_data
The HPS is nearly configures, at last apply some auto functions:
System → Assign Base Addresses
System → Assign Interrupt Numbers
System → Assign Custom Instruction Opcodes
System → Create Global Reset Network
Achtung beim Schritt HDL generate
The Hardware Description language file is obtained by pressing Generate HDL in the bottom right corner of the
window.
A new window opens, - Generation. In this window, under Synthesis, select via Dropdown Menu in which
Hardware Language your HDL will be created, Verilog or VHDL, check Create block symbole file (.bsf) and
uncheck Create timing and resource estimate... .
Press in the bottom left Generate and a saving dialogue opens, reminding to save the design. Name the file, this
guide designates the file PlatformEditorHPS.qsys , press Save and wait until the design is saved. The window shows
the message - Save System: Completed successfully.
Press Close and immediately a new window opens, in it press Generate and wait for the
message - Generation: Completed successfully - to show up, press Close to shut the window down.
Close the Plattform Designer by pressing Finish. A notification appears, reminding to add files into the project,
press OK.
To add the file(s), open a new dialogue window via Project → Add/Remove Files in Project ... . The following
window opens, in it, click onto to button with 3 dots / inside the red rectangle.
The - Select File - window opens, point along the path project > PlatformEditorHPS > synthesis to the file PlatformEditorHPS.qip,
double click onto it to select it, the window closes, close the - Settings - HPSexample - window by clicking the button OK in the
bottom left.
In Project Navigator, upper left column in Quartus, use the Drop-down Menu for changing from Hierarchy to Files.
The file PlatformEditorHPS.qip is now visible and via right click onto the file, it must be Set as Top-Level Entity.
Lastly, a TCL-Script needs to be run. In Quartus click onto Tools → Tcl Scripts ... . The window - Tcl Scripts - opens, select
Project1 → PlatformEditorHPS → synthesis → submodules → hps_sdram_p0_pin_assignments.tcl , click Run to execute the script.
After the script finishes, confirm the notification and close the previous window through close.
Hit Processing → Start Compilation and wait until the compilation has finished , this must finish without any error,
warnings and critical warnings are expected.
Now the project folder contains the following.
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