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Table of contents


Linux with basic periphery of TE0807 Starterkit (TEBF0808 Carrier).

Refer to for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2019.2
  • TEBF0808
  • Linux
  • USB
  • ETH
  • MAC from EEPROM
  • PCIe
  • SATA
  • SD
  • I2C
  • DP
  • user LED access
  • Modified FSBL for Si5338 programming
  • Special FSBL for QSPI Programming

Revision History

DateVivadoProject BuiltAuthorsDescription
John Hartfiel
  • add missing linux Boot.bin
  • small update for  SI configuration (FSBL)
John Hartfiel
  • 2019.2 update
  • Vitis support
  • FSBL SI programming procedure update 
  • petalinux device tree and u-boot update
John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
  • ES2 prebuilt files are not included
John Hartfiel
  • new assembly variant
John Hartfiel
  • small petalinux changes
  • IO renaming
  • PL Design changes
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
John Hartfiel
  • solved Linux Flash issue
John Hartfiel
  • same CLK for VIO
John Hartfiel
  • solved JTAG/Linux issue
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaround/SolutionTo be fixed version
Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 update
USB UART Terminal is blocked / SDK Debugging is blockedThis happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is nessecary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal
Solved with 20180205 update
Known Issues



Vitis2019.2needed, Vivado is included into Vitis installation
SI ClockBuilder Pro---optional


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0807-01-07EV-ES   es2_2gb      REV01    2GB      64GB       NA         NA     Not longer supported by vivado
TE0807-02-07EV-1E   7ev_1e_4gb   REV02    4GB      64GB       NA         NA     NA                               
TE0807-02-07EV-1EK  7ev_1e_4gb   REV02    4GB      64GB       NA         NA     with heat sink                 
TE0807-02-4BE21-A   4eg_1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DE21-A   7ev_1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DI21-C   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     without encryption             
TE0807-02-7DI21-A   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-4AI21-A   4cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-5AI21-A   5cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7AI21-A   7cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DI24-A   7ev_1i_4gb   REV02    4GB      512MB      NA         NA     NA                               
TE0807-02-7DE21-AK  7ev_1e_4gb   REV02    4GB      128MB      NA         NA     with heat sink             
Hardware Modules

Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.

Design supports following carriers:

Carrier ModelNotes
TEBF0808Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended
Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes

Additional Hardware


For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

SI5345<design name>/misc/Si5345SI5345 Project with current PLL Configuration<design name>/sd/Additional Initialization Script for Linux
Additional design sources





BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)


Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/ and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which ends with *_tebf0808
  5. Create XSA and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
  7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
    1. prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
  8. Generate Programming Files with Vitis
    1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis


For basic board setup, LEDs... see: TEBF0808 Getting Started


Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/ and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated


Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0803" possible
  4. Copy image.ub on SD-Card
    1. use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    2. or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Set Boot Mode to QSPI-Boot and insered SD.
    1. Depends on Carrier, see carrier TRM.
    2. TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area


  1. Copy image.ub and Boot.bin on SD-Card.
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.


Not used on this Example.


  1. Prepare HW like described on section TE0807 StarterKit#Programming
  2. Connect UART USB (JTAG XMOD)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
    Note: See TRM of the Carrier, which is used.
  4. (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
  5. (Optional) Connect Sata Disc
  6. (Optional) Connect DisplayPort Monitor (List of usable Monitors:
  7. (Optional) Connect Network Cable
  8. Power On PCB
    Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.


  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. ETH0 works with udhcpc
    3. USB type  "lsusb" or connect USB device
    4. PCIe type "lspci"
  4. Option Features
    1. Webserver to get access to Zynq
      1. insert IP on web browser to start web interface
    2. scripts
      1. add script on SD, content will be load automatically on startup (template included in ./misc/SD)

Vivado Hardware Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

  • Control:
    • LEDs: XMOD 2(without green dot) and HD LED are accessible.
    • CAN_S

Vivado Hardware Manager

System Design - Vivado

Block Design

Block Design

PS Interfaces

Activated interfaces:

PS Interfaces


Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

#System Controller IP

#J3:31 LED_HD
set_property PACKAGE_PIN K11 [get_ports BASE_sc0]
set_property PACKAGE_PIN E14 [get_ports BASE_sc5]
set_property PACKAGE_PIN C12 [get_ports BASE_sc6]
set_property PACKAGE_PIN D12 [get_ports BASE_sc7]
set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN K13 [get_ports BASE_sc11]
set_property PACKAGE_PIN A13 [get_ports BASE_sc12]
set_property PACKAGE_PIN A14 [get_ports BASE_sc13]
set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
#J3:46 CAN S
set_property PACKAGE_PIN A12 [get_ports BASE_sc16]
set_property PACKAGE_PIN B12 [get_ports BASE_sc17]
#J3:50 CAN TX 
set_property PACKAGE_PIN B14 [get_ports BASE_sc18]
#J3:52 CAN RX 
set_property PACKAGE_PIN C14 [get_ports BASE_sc19]

set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]

#set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]

# Audio Codec
#LRCLK        J3:49 B47_L9_N
#BCLK        J3:51 B47_L9_P
#DAC_SDATA    J3:53 B47_L7_N
#ADC_SDATA    J3:55 B47_L7_P
set_property PACKAGE_PIN G14 [get_ports LRCLK ]
set_property PACKAGE_PIN H14 [get_ports BCLK ]
set_property PACKAGE_PIN C13 [get_ports DAC_SDATA ]
set_property PACKAGE_PIN D14 [get_ports ADC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]

Software Design - Vitis

For SDK project creation, follow instructions from:



SDK template in ./sw_lib/sw_apps/ available.


TE modified 2019.2 FSBL


  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5345 Configuration
    • OTG+PCIe Reset over MIO
    • I2C MUX for EEPROM MAC


TE modified 2019.2 FSBL


  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


Xilinx default PMU firmware.


Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.


U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:


Start with petalinux-config or petalinux-config --get-hw-description




Start with petalinux-config -c u-boot



  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set










Change platform-top.h:


Device Tree

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;

/* notes:
serdes: // PHY TYP see: dt-bindings/phy/phy.h

/* default */

/* SD */

&sdhci1 {
	// disable-wp;


/* USB  */

&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    phy-names = "usb2-phy","usb3-phy";
    phys = <&lane1 4 0 2 100000000>;
    maximum-speed = "super-speed";

/* ETH PHY */

&gem3 {
	phy-handle = <&phy0>;
	phy0: phy0@1 {
		device_type = "ethernet-phy";
		reg = <1>;

/* QSPI */

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;

/* I2C */

&i2c0 {
    i2cswitch@73 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x73>;
        i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        i2c@1 { // SFP TEBF0808 PCF8574DWR
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        i2c@2 { // PCIe
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        i2c@3 { // SFP1 TEBF0808
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        i2c@4 {// SFP2 TEBF0808
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        i2c@5 { // TEBF0808 EEPROM
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
            eeprom: eeprom@50 {
	            compatible = "atmel,24c08";
	            reg = <0x50>;
        i2c@6 { // TEBF0808 FMC  
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        i2c@7 { // TEBF0808 USB HUB
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
    i2cswitch@77 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x77>;
        i2c@0 { // TEBF0808 PMOD P1
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        i2c@1 { // i2c Audio Codec
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
            adau1761: adau1761@38 {
                compatible = "adi,adau1761";
                reg = <0x38>;
        i2c@2 { // TEBF0808 Firefly A
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        i2c@3 { // TEBF0808 Firefly B
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        i2c@4 { //Module PLL Si5338 or SI5345
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        i2c@5 { //TEBF0808 CPLD
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        i2c@6 { //TEBF0808 Firefly PCF8574DWR
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        i2c@7 { // TEBF0808 PMOD P3
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;


Start with petalinux-config -c kernel


  • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)



Start with petalinux-config -c rootfs


  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y (for web server app)
  • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)


See: \os\petalinux\project-spec\meta-user\recipes-apps\


Script App to load from SD Card if available.


Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software


File location <design name>/misc/Si5345/Si5345-*.slabtimeproj

General documentation how you work with these project will be available on Si5345

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument Revision



  • Design update
2020-01-27v.17John Hartfiel
  • new assembly variants
  • Release 2019.2
2019-05-22v.16John Hartfiel
  • Release 2018.3


v.13John Hartfiel
  • Release 2018.2


v.12John Hartfiel
  • Design update


v.10John Hartfiel
  • Update known issues


v.9John Hartfiel
  • Design update
2018-01-29v.4John Hartfiel
  • Update known issues
2018-01-18v.3John Hartfiel
  • Release 2017.4

Document change history.

Legal Notices

Data Privacy

Please also note our data protection declaration at

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

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Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

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Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).


Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.


Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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