Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Notes :
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Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.
Notes :
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Notes :
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Notes :
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Notes :
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Notes :
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Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
*used as reference |
Design supports following carriers:
*used as reference |
Additional HW Requirements:
|
Notes :
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
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Notes :
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Notes :
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
This step depends on Xilinx Device/Hardware for Zynq-7000 series
for ZynqMP
for ...
|
Generate Programming Files with Vitis
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Note:
|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0720 (optional) |
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup |
Not used on this Example.
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. |
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM FSBL from QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for native FPGA ... |
select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
petalinux login: root Password: root |
Note: Wait until Linux boot finished |
You can use Linux shell now.
i2cdetect -y -r 0 (check I2C 0 Bus) i2cdetect -y -r 1 (check I2C 1 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) |
Note:
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Monitoring: PHY LED
Note:
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Note:
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Activated interfaces:
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# # Common BITGEN related settings for TE0720 SoM # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design |
# set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
# # Constraints for System controller support logic # set_property PACKAGE_PIN K16 [get_ports PL_pin_K16] set_property PACKAGE_PIN K19 [get_ports PL_pin_K19] set_property PACKAGE_PIN K20 [get_ports PL_pin_K20] set_property PACKAGE_PIN L16 [get_ports PL_pin_L16] set_property PACKAGE_PIN M15 [get_ports PL_pin_M15] set_property PACKAGE_PIN N15 [get_ports PL_pin_N15] set_property PACKAGE_PIN N22 [get_ports PL_pin_N22] set_property PACKAGE_PIN P16 [get_ports PL_pin_P16] set_property PACKAGE_PIN P22 [get_ports PL_pin_P22] # # If Bank 34 is not 3.3V Powered need change the IOSTANDARD # set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16] |
Note:
|
For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2020.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2020.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
TE modified 2020.2 FSBL
General:
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
Module Specific:
TE modified 2020.2 FSBL
General:
Hello World App in Endless loop.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Note:
|
For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
Note: for variants with 256MB DDR only, change NET Boot Address to 0x8000000 on boot.src file
Start with petalinux-config -c u-boot
Changes:
Change platform-top.h:
#include <configs/zynq-common.h> #include <configs/platform-auto.h> #define CONFIG_PREBOOT "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp" |
/include/ "system-conf.dtsi" / { }; /* default */ /* QSPI PHY */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* ETH PHY */ &gem0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0>; }; }; }; /* USB PHY */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; //compatible = "usb-nop-xceiv"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; //dr_mode = "peripheral"; usb-phy = <&usb_phy0>; }; /* I2C need I2C1 connected to te0720 system controller ip */ &i2c1 { iexp@20 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x20>; gpio-controller; }; iexp@21 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x21>; gpio-controller; }; rtc@6F { // Real Time Clock compatible = "isl12022"; reg = <0x6F>; }; }; |
Must be add manually, see template
Start with petalinux-config -c kernel
Changes:
Start with petalinux-config -c rootfs
Changes:
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
Script App to load init.sh from SD Card if available.
Webserver application suitable for Zynq access. Need busybox-httpd
Note: |
No additional software is needed.
To get content of older revision got to "Change History" of this page and select older document revision number.
|
|
|
|
Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
|
Important General Note:
|
Notes :
|
Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.
Notes :
|
|
Notes :
|
|
Notes :
|
|
Notes :
|
|
Notes :
|
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
*used as reference |
Design supports following carriers:
*used as reference |
Additional HW Requirements:
|
Notes :
|
For general structure and usage of the reference design, see Project Delivery - Xilinx devices
|
|
Notes :
|
|
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
|
Reference Design is available on:
Notes :
|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
This step depends on Xilinx Device/Hardware for Zynq-7000 series
for ZynqMP
for ...
|
Generate Programming Files with Vitis
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Note:
|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0720 (optional) |
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup |
Not used on this Example.
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. |
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM FSBL from QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for native FPGA ... |
select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
petalinux login: root Password: root |
Note: Wait until Linux boot finished |
You can use Linux shell now.
i2cdetect -y -r 0 (check I2C 0 Bus) i2cdetect -y -r 1 (check I2C 1 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) |
Note:
|
Monitoring: PHY LED
Note:
|
Note:
|
Activated interfaces:
|
# # Common BITGEN related settings for TE0720 SoM # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design |
# set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
# # Constraints for System controller support logic # set_property PACKAGE_PIN K16 [get_ports PL_pin_K16] set_property PACKAGE_PIN K19 [get_ports PL_pin_K19] set_property PACKAGE_PIN K20 [get_ports PL_pin_K20] set_property PACKAGE_PIN L16 [get_ports PL_pin_L16] set_property PACKAGE_PIN M15 [get_ports PL_pin_M15] set_property PACKAGE_PIN N15 [get_ports PL_pin_N15] set_property PACKAGE_PIN N22 [get_ports PL_pin_N22] set_property PACKAGE_PIN P16 [get_ports PL_pin_P16] set_property PACKAGE_PIN P22 [get_ports PL_pin_P22] # # If Bank 34 is not 3.3V Powered need change the IOSTANDARD # set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16] |
Note:
|
For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2020.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2020.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
TE modified 2020.2 FSBL
General:
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
Module Specific:
TE modified 2020.2 FSBL
General:
Hello World App in Endless loop.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Note:
|
For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
Note: for variants with 256MB DDR only, change NET Boot Address to 0x8000000 on boot.src file
Start with petalinux-config -c u-boot
Changes:
Change platform-top.h:
#include <configs/zynq-common.h> #include <configs/platform-auto.h> #define CONFIG_PREBOOT "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp" |
/include/ "system-conf.dtsi" / { }; /* default */ /* QSPI PHY */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* ETH PHY */ &gem0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0>; }; }; }; /* USB PHY */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; //compatible = "usb-nop-xceiv"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; //dr_mode = "peripheral"; usb-phy = <&usb_phy0>; }; /* I2C need I2C1 connected to te0720 system controller ip */ &i2c1 { iexp@20 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x20>; gpio-controller; }; iexp@21 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x21>; gpio-controller; }; rtc@6F { // Real Time Clock compatible = "isl12022"; reg = <0x6F>; }; }; |
Must be add manually, see template
Start with petalinux-config -c kernel
Changes:
Start with petalinux-config -c rootfs
Changes:
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
Script App to load init.sh from SD Card if available.
Webserver application suitable for Zynq access. Need busybox-httpd
Note: |
No additional software is needed.
To get content of older revision got to "Change History" of this page and select older document revision number.
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