Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Notes :
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Refer to http://trenz.org/te0818-info for the current online version of this manual and other available documentation.
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Note: Design contains also Board Part Files for TE0818 only configuration, this board part files are not used for this reference design.
Design supports following carriers:
*used as reference |
Additional HW Requirements:
*used as reference |
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For general structure and usage of the reference design, see Project Delivery - AMD devices
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow Important: Use Board Part Files, which ends with *_tebf0818 |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
This step depends on Xilinx Device/Hardware for Zynq-7000 series
for ZynqMP
for Microblaze
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Generate Programming Files
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Note:
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For basic board setup, LEDs... see: TEBF0818 Getting Started
Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Option for Boot.bin on QSPI Flash
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp hello_te0818 |
Not used on this example.
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. |
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for Microblaze with Linux 1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available) 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR for native FPGA ... |
select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
# password disabled petalinux login: root Password: root |
Note: Wait until Linux boot finished |
You can use Linux shell now.
i2cdetect -y -r 0 (check I2C 0 Bus, replace 0 with other bus number is also possible) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) lspci (PCIe check) |
Option Features
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
Note:
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Note:
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Activated interfaces:
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
#System Controller IP #LED_HD SC0 J3:C13 #LED_XMOD SC17 J3:B19 #CAN RX SC19 J3:B23 #CAN TX SC18 J3:B22 #CAN S SC16 J3:B18 #HDIO_SC0 J14 set_property PACKAGE_PIN J14 [get_ports BASE_sc0] #HDIO_SC5 G13 set_property PACKAGE_PIN G13 [get_ports BASE_sc5] #HDIO_SC6 J15 set_property PACKAGE_PIN J15 [get_ports BASE_sc6] #HDIO_SC7 K15 set_property PACKAGE_PIN K15 [get_ports BASE_sc7] #HDIO_SC10 A15 set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io] #HDIO_SC11 B15 set_property PACKAGE_PIN B15 [get_ports BASE_sc11] #HDIO_SC12 C13 set_property PACKAGE_PIN C13 [get_ports BASE_sc12] #HDIO_SC13 C14 set_property PACKAGE_PIN C14 [get_ports BASE_sc13] #HDIO_SC14 E13 set_property PACKAGE_PIN E13 [get_ports BASE_sc14] #HDIO_SC15 E14 set_property PACKAGE_PIN E14 [get_ports BASE_sc15] #HDIO_SC16 A13 set_property PACKAGE_PIN A13 [get_ports BASE_sc16] #HDIO_SC17 B13 set_property PACKAGE_PIN B13 [get_ports BASE_sc17] #HDIO_SC18 A14 set_property PACKAGE_PIN A14 [get_ports BASE_sc18] #HDIO_SC19 B14 set_property PACKAGE_PIN B14 [get_ports BASE_sc19] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19] # Audio Codec #LRCLK J3:49 B47_L9_N #BCLK J3:51 B47_L9_P #DAC_SDATA J3:53 B47_L7_N #ADC_SDATA J3:55 B47_L7_P #LRCLK G14 set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ] #BCLK G15 set_property PACKAGE_PIN G15 [get_ports I2S_bclk ] #DAC_SDATA E15 set_property PACKAGE_PIN E15 [get_ports I2S_sdin ] #ADC_SDATA F15 set_property PACKAGE_PIN F15 [get_ports I2S_sdout ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ] # MGTs # F25 MGT_128_CLK0_P -> U5,45 -> Si5345 -> out6 # F26 MGT_128_CLK0_N -> U5,44 -> Si5345 -> out6 # D25 MGT_128_CLK1_P -> B2B,J2-A7 -> floating # D26 MGT_128_CLK1_N -> B2B,J2-A6 -> floating # R8 MGT_228_CLK0_P -> B2B,J3-B27 -> TEBF0818-01_FMC_J5E-D5 # R7 MGT_228_CLK0_N -> B2B,J3-B26 -> TEBF0818-01_FMC_J5E-D4 # N8 MGT_228_CLK1_P -> U5,35 -> Si5345 -> out3 # N7 MGT_228_CLK1_N -> U5,34 -> Si5345 -> out3 # L8 MGT_229_CLK0_P -> B2B,J3-C26 -> TEBF0818-01_FMC_J5E-B21 # L7 MGT_229_CLK0_N -> B2B,J3-C25 -> TEBF0818-01_FMC_J5E-B20 # J8 MGT_229_CLK1_P -> U5,31 -> Si5345 -> out2 # J7 MGT_229_CLK1_N -> U5,30 -> Si5345 -> out2 # G8 MGT_230_CLK0_P -> U5,28 -> Si5345 -> out1 # G7 MGT_230_CLK0_N -> U5,27 -> Si5345 -> out1 # E8 MGT_230_CLK1_P -> B2B,J3-D27 -> TEBF0818-01_CLK7_P -> B2B,J2-D5 -> U5,51 -> Si5345 -> out7 # E7 MGT_230_CLK1_N -> B2B,J3-D26 -> TEBF0818-01_CLK7_N -> B2B,J2-D6 -> U5,50 -> Si5345 -> out7 set_property PACKAGE_PIN F25 [get_ports {MGT_CLK_IN_clk_p[0]}] set_property PACKAGE_PIN D25 [get_ports {MGT_CLK_IN_clk_p[1]}] set_property PACKAGE_PIN R8 [get_ports {MGT_CLK_IN_clk_p[2]}] set_property PACKAGE_PIN N8 [get_ports {MGT_CLK_IN_clk_p[3]}] set_property PACKAGE_PIN L8 [get_ports {MGT_CLK_IN_clk_p[4]}] set_property PACKAGE_PIN J8 [get_ports {MGT_CLK_IN_clk_p[5]}] set_property PACKAGE_PIN G8 [get_ports {MGT_CLK_IN_clk_p[6]}] set_property PACKAGE_PIN E8 [get_ports {MGT_CLK_IN_clk_p[7]}] |
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For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example ---------------------------------------------------------- scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2023.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2023.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: ---------------------------------------------------------- fsblTE modified 2023.2 FSBL General:
Module Specific:
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2023.2 FSBL General:
Module Specific:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: ---------------------------------------------------------- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
TE modified 2023.2 FSBL
General:
Module Specific:
Xilinx default PMU firmware.
Hello TE0818 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Note:
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For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
Start with petalinux-config -c u-boot
Changes:
Change platform-top.h:
#no changes |
/include/ "system-conf.dtsi" /*------------------ gtr --------------------*/ //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver / { refclk3:psgtr_dp_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <27000000>; }; refclk2:psgtr_pcie_usb_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <100000000>; }; refclk1:psgtr_sata_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <150000000>; }; //refclk0:psgtr_unused_clock { // compatible = "fixed-clock"; // #clock-cells = <0x00>; // clock-frequency = <100000000>; //}; }; &psgtr { clocks = <&refclk1 &refclk2 &refclk3>; /* ref clk instances used per lane */ clock-names = "ref1\0ref2\0ref3"; }; /*------------------ SD --------------------*/ &sdhci0 { // disable-wp; no-1-8-v; }; &sdhci1 { // disable-wp; no-1-8-v; }; /*------------------- USB --------------------*/ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; maximum-speed = "super-speed"; }; /*------------------ ETH PHY --------------------*/ &gem3 { /delete-property/ local-mac-address; phy-handle = <&phy0>; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /*----------------- SATA PHY --------------------*/ &sata { ceva,p0-burst-params = <0x13084a06>; ceva,p0-cominit-params = <0x18401828>; ceva,p0-comwake-params = <0x614080e>; ceva,p0-retry-params = <0x96a43ffc>; ceva,p1-burst-params = <0x13084a06>; ceva,p1-cominit-params = <0x18401828>; ceva,p1-comwake-params = <0x614080e>; ceva,p1-retry-params = <0x96a43ffc>; }; /*-------------------- QSPI ---------------------*/ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; spi-max-frequency = <90000000>; }; }; /*------------------ I2C --------------------*/ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@0 { // MCLK TEBF0818 SI5338A, 570FBB000290DG_unassembled reg = <0>; }; i2c@1 { // SFP TEBF0818 PCF8574DWR reg = <1>; }; i2c@2 { // PCIe reg = <2>; }; i2c@3 { // SFP1 TEBF0818 reg = <3>; }; i2c@4 {// SFP2 TEBF0818 reg = <4>; }; i2c@5 { // TEBF0818 EEPROM reg = <5>; eeprom: eeprom@50 { compatible = "microchip,24aa025", "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; }; i2c@6 { // TEBF0818 FMC reg = <6>; }; i2c@7 { // TEBF0818 USB HUB reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0818 PMOD P1 reg = <0>; }; i2c@1 { // i2c Audio Codec reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // TEBF0818 Firefly A reg = <2>; }; i2c@3 { // TEBF0818 Firefly B reg = <3>; }; i2c@4 { //Module PLL Si5338 or SI5345 reg = <4>; }; i2c@5 { //TEBF0818 CPLD reg = <5>; }; i2c@6 { //TEBF0818 Firefly PCF8574DWR reg = <6>; }; i2c@7 { // TEBF0818 PMOD P3 reg = <7>; }; }; }; |
Start with petalinux-config -c kernel
Changes:
Start with petalinux-config -c rootfs
Changes:
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5345) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src" |
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
Webserver application suitable for ZynqMP access. Need busybox-httpd
Note: |
File location "<project folder>\misc\PLL\Si5345_*\Si5345-*.slabtimeproj"
General documentation how you work with this project will be available on Si5345
Si5345A-B-GM is no longer supported by the latest Skyworks Clockbuilder Pro software. |
To get content of older revision go to "Change History" of this page and select older document revision number.
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