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Overview

The Trenz Electronic TEF1001 FPGA board is a PCI Express form factor card integrating the Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC. The FPGA-board is designed for high system resources and intended for use in applications with high demands on system performance and throughput. To extent the board with standard DDR3 SDRAM memory module, there is a 204-pin SODIMM socket with 64bit databus width on the board present. Highspeed data transmission is enabled by the 4 lane PCIe Gen 2 interface.

The board offers a HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard FPGA Mezzanine cards and modules. Other interface connectors found on-board include JTAG for accessing FPGA and on-board System Controller CPLD.

The TEF1001 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host system to meet the power supply requirements.

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Refer to http://trenz.org/tef1001-info for the current online version of this manual and other available documentation.

Key Features

• Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC
• Large number of configurable I/Os are provided via HPC FMC connector
  • 4 GTX high-performance transceiver
  • 2x MGT transceiver clock inputs
  • 160 FPGA I/O's (80 LVDS pairs)
• On-board high-efficiency switch-mode DC-DC converters
• Lattice MachXO2 LCMXO2-1200HC System Controller CPLD
• 10x User LEDs
• PCI Express x8 connector with 4 lane PCIe Gen 2 interface
• ANSI Vita 57.1 FMC High Pin Count (HPC) connector
• DDR3 SODIMM SDRAM socket with 64bit databus width
• 256Mbit (32MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
  • FPGA
  • JTAG port (SPI indirect, bus width x4)
• FPGA configuration through:
  • JTAG connector
  • Quad SPI Flash memory

• Clocking

  • Si5338 programmable quad PLL clock generator - 4 outputs for MGT and PL clocks

  • 200MHz oscillator for DDR3 bank

• System management and power sequencing
  
  

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Main Components

1. Xilinx Kintex XC7K-2FBG676I FPGA SoC, U6
2. ANSI/VITA 57.1 compliant FMC HPC connector, J2
3. Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
4. PCIe x8 connector, J1
5. DDR3 SODIMM 204-pin socket, U2
6. 6-pin 12V power connector, J5
7. Step-down DC-DC converter @1.5V and @4V (LT LTM4676A), U3
8. Step-down DC-DC converter @1.0V (LT LTM4676A), U4
9. 256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
10. 10x Green user LEDs connected to FPGA, D1 ... D10
11. 4-wire PWM fan connector, J4
12. User button, S2
13. FPGA JTAG connector, J9
14. 4bit DIP switch, S1
15. I²C header for LTM4676A DC-DC converter, J10
16. System Controller CPLD JTAG header, J8
17. 1x Green LED connected to SC CPLD, D11
18. 2-pin 5V FAN header, J6
19. System Controller CPLD (Lattice Semiconductor LCMXO2-1200HC), U5
20. 6A PowerSoC DC-DC converter @FMC_VADJ (Altera EN5365QI), U7
21. 4A PowerSoC DC-DC converter @3.3V (3V3FMC) (Altera EN6347QI), U15
22. LDO converter @1.2V (MGTAVTT_FPGA) (TI TPS74401RGW), U17
23. LDO converter @1.0V (MGTAVCC_FPGA) (TI TPS74401RGW), U18
24. 4A PowerSoC DC-DC converter @1.8V (Altera EN6347QI), U7

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

By default the configuration mode pins M[2:0] of the FPGA are set to QSPI mode (Master SPI), hence the FPGA is configured from QSPI Flash memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI Flash memory.

Signals, Interfaces and Pins

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FMC HPC Connector I/Os

I/O signals connected to the SoCs I/O bank and FMC connector J2:

Table 2: General overview of FPGA's PL I/O signals connected to the FMC connector

For detailed information about the pin out, please refer to the Pin-out Tables.

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PCI Express Interface

The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots and has a data transmission capability which meets PCIe Gen. 2. See next section for the overview of FPGA MGT lanes routed to the PCIe interface.

MGT Lanes

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. The MGT lanes are connected to the FMC connector and to the PCIe x8 connector. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:

Table 3: FPGA to B2B connectors routed MGT lanes overview

Below are listed MGT banks reference clock sources:

Table 4: MGT reference clock sources

JTAG Interface

There are three JTAG interfaces available on the TEF1001 board:

Table 5: JTAG interface signals

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Table 6: System Controller CPLD I/O pins

For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the module's SC CPLD or into its bitstream file.

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Quad SPI Interface

Quad SPI Flash memory interface is connected to the FPGA bank 14, QSPI clock is provided by FPGA config bank 0.

Table 7: Quad SPI interface signals and connections

I2C Interface

On-module I²C interface is routed  from PL bank 14 I/O pins (FPGA_IIC_SDA, FPGA_IIC_SCL and FPGA_IIC_OE) to the I²C interface of SC CPLD U5 which works as I²C switch with the FPGA as I²C-Master. The I²C interfaces of the on-board peripherals are muxed to the FPGA I²C interface via SC CPLD U5. Also the FAN control of the 4-wire PWM FAN connector J4 can be controlled via I²C from FPGA. For detailed information, refer to the reference page of the SC CPLD firmware of this module, section I²C.

Table 8: I²C slave device addresses

FAN Connectors

The TEF1001 board offers two FAN connectors for cooling the FPGA device and on built-in FAN for the FMC modules.

Table 9: FAN connectors

On-board Peripherals

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System Controller CPLD

The System Controller CPLD (U5) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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DDR3 SDRAM SODIMM Socket

The TEF1001 board supports additional DDR3 SODIMM via 204-pin socket U2. The DDR3 memory interface has a 64bit wide databus and is routed to the FPGA banks 32, 33 and 34.

The reference clock signal for the DDR3 interface is generated by the 200.0000MHz MEMS oscillator U1 and is applied to the FPGA bank 33.

There is also a I²C interface between the System Controller CPLD U5 and the DDR3 SODIMM memory socket U2.

Quad SPI Flash Memory

A 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U13) to generate various reference clocks for the module.

 Table 10: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed

Oscillators

The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Table 11: Reference clock signals

On-board LEDs

Table 11: On-board LEDs

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 12: Typical power consumption

 * TBD - To Be Determined soon with reference design setup.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

Power-On Sequence

The TE0841 SoM meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Power Rails

Table 13: Module power rails

Bank Voltages

Table 14: Module PL I/O bank voltages

Variants Currently In Production

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See also the current available variants on the Trenz Electronic shop page

Technical Specifications

Absolute Maximum Ratings

Table 16: Module absolute maximum ratings

Recommended Operating Conditions

Table 17: Module recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Board size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.

• PCB thickness: ca. 1.55 mm.

• The board meets the PCIe standard specifications for the dimensions

All dimensions are given in millimeters.

Revision History

Hardware Revision History

Table 18: Module hardware revision history

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Date	Revision	Contributors	Description
			Initial document

Table 18: Document change history

Disclaimer

02 Sept 2017