TE0803 TRM

Overview

The Trenz Electronic TE0803 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+, max. 8 GByte DDR4 SDRAM with 64-Bit width data bus connection, max. 512 MByte SPI Boot Flash memory for configuration and operation, up to 8 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

All this in a compact 5.2 x 7.6 cm form factor, at the most competitive price

Key Features

• Xilinx Zynq UltraScale+ MPSoC 784 pin package (options: ZU2CG, ZU2EG, ZU3CG, ZU3EG, ZU4CG, ZU4EV)
• Memory
  - 64-Bit DDR4, 8 GByte maximum
  - Dual SPI boot Flash in parallel, 512 MByte maximum
• User I/O
  - 65 x MIO, 48 x HD (all),  156 x HP (3 banks)
  - Serial transceiver: 4 x GTR (+ 4 x GTH transceiver with ZU4CG or ZU4EV MPSoC)
  - Transceiver clocks inputs and outputs
  - PLL clock generator inputs and outputs
• Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
• B2B connectors: 4 x 160 pin
• Si5338A - 4 output PLL
• All power supplies on board, single 3.3V power source required
  - LP, FP, PL separately controlled power domains
• Support for all boot modes (except NAND) and scenarios
• Support for any combination of PS connected peripherals

Block Diagram

Figure 1: TE0803-01 Block Diagram

Main Components

Figure 2: TE0803-01 MPSoC module

1. Xilinx ZYNQ UltraScale+ MPSoC, U1
2. 2-Input AND Gate, U39
3. Red LED (DONE), D1
4. 256Mx16 DDR4-2400 SDRAM, U12
5. 256Mx16 DDR4-2400 SDRAM, U9
6. 256Mx16 DDR4-2400 SDRAM, U2
7. 256Mx16 DDR4-2400 SDRAM, U3
8. 12A PowerSoC DC-DC converter, U4
9. 1.5A LDO DC-DC converter, U10
10. 1.5A LDO DC-DC converter, U8
11. Voltage monitor circuit, U41
12. 0.35A LDO DC-DC converter, U26
13. 0.35A LDO DC-DC converter, U27
14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
18. 4-channel programmable PLL clock generator, U5
19. Low-power programmable oscillator @ 25.000000 MHz, U5
20. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
21. 256 Mbit serial NOR Flash memory, U7
22. 256 Mbit serial NOR Flash memory, U17

Initial Delivery State

Table 1: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

Board to Board (B2B) connectors

The TE0803 MPSoC SoM has four Board to Board (B2B) connectors with 160 contacts per connector.

Each connector has a specific arrangement of the signal-pins, which are grouped together in categories related to their functionalities and to their belonging to particular units of the Zynq UltraScale+ MPSoC like I/O-banks, interfaces and Gigabit transceivers
or to the on-board peripherals.

Following table lists the I/O-bank signals, which are routed from the MPSoC's PL and PS banks as LVDS pairs or single ended I/O's to the B2B connectors.

Table 2: B2B connector pin-outs of available PL and PS banks of the TE0803-01 SoM

              1) Bank 25 at XCZU2 / XCZU3, else Bank 45 at XCZU4 / XCZU5

              2) Bank 26 at XCZU2 / XCZU3, else Bank 46 at XCZU4 / XCZU5

All MIO banks are powered from on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.

For detailed information about the B2B pin-out, please refer to the Pin-out table. 

The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.

MGT Lanes

The B2B connectors J1 and J2 provide also access to the MGT banks of the Zynq UltraScale+ MPSoC. There are 8 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).

The MGT banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT lanes are available on the B2B connectors:

Table 3: B2B connector pin-outs of available MGT lanes of the MPSoC

              1) Bank 224 only available at XCZU4 / XCZU5 MPSoC.

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage 'PS_1V8'.

Table 4: B2B connector pin-out of JTAG interface

Configuration Bank Control Signals

The Xilinx Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B-connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

Table 5: B2B connector pin-out of MPSoC's PS configuration bank

Analog Input

The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

Table 6: B2B connector pin-out of analog input pins

Quad SPI Interface

Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO0..MIO5 and MIO7..MIO12.

Table 7: MIO pin assignment of the Quad SPI Flash memory ICs

Boot Process

The boot source of the Zynq UltraScale+ MPSoC can be selected via 4 dedicated pins, which generate a 4-bit code to select the boot mode. The pins are accessible on B2B connector J2:

Table 8: Boot mode pins on B2B connector J2

Following boot modes are possible on the TE0803 UltraScale+ MPSoC module by generating the corresponding 4-bit code with pins 'PS_MODE0' ... 'PS_MODE3' (little-endian alignment):

Table 9: Selectable boot modes by dedicated boot mode pins

For functional details see ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).

On-board Peripherals

Flash

The TE0803 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.

Table 10: Peripherals connected to the PS MIO pins

DDR4 SDRAM

The TE0803-01 SoM is equipped with with four DDR4-2400 SDRAM modules with up to 8 GByte of memory. The SDRAM modules are connected to the Zynq MPSoC's PS DDR controller (bank 504) via 64-bit wide  data bus.

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information, if the specific Zynq UltraScale+ MPSoC chip on module supports the maximum data transmission rate of 2400 MByte/s.

Programmable PLL Clock Generator

Following table illustrates on-board Si5338A programmable clock multiplier chip inputs and outputs:

Table 11: Programmable PLL clock generator input/output

The Si5338A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5338A data sheet.

Table 12: B2B connector pin-out of Si5338A control interface

Si5338A OTP can only be programmed two times, as different user configurations may require different setup, TE0803 is normally shipped with blank OTP.
Refer to Si5338A datasheet for more information.

Clocking

The TE0803-01 SoM is equipped with two on-board oscillators to provide the Zynq MPSoC's PS configuration bank 503 with reference clock signals.

Table 13: Reference clock-signals to PS configuration bank 503

On-board LEDs

Table 14: LED's description

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 15: Maximum current of power supplies. *To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0803 module equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular external DC-DC converters.

The Processing System contains three Power Domains:

• Battery Power Domain (BBRAM and RTC)
• Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
• Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0803 SoM, following Power Domains can be powered up individually with power rails available on the B2B connectors:

• Full-Power Domain, supplied by power rail 'DCDCIN'
• Low-Power Domain, supplied by power rail 'LP_DCDC'
• Programmable Logic, supplied by power rail 'PL_DCIN'
• Battery Power Domain, supplied by power rail 'PS_BATT'

Each Power Domain has its own "Enabling"- and "Power Good"-signals. The power rail 'GT_DCDC' is only necessary for variants of the TE0803 module with the Xilinx Zynq UltraScale+ ZU4CG or ZU4EV MPSoC to generate the voltages for the available Xilinx GTH unit.

Power Distribution Dependencies

The power rails 'DCDCIN', 'LP_DCDC', 'PL_DCIN', 'PS_BATT' have to be powered up on the assigned pins of the B2B connectors as listed on the section "Power Rails". Except 'PS_BATT' (see section "Recommended Operation Conditions"), all power-rails can be powered up, with 3.3V power sources, also shared, if Power Domain control is not required.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

Figure 3: Power Distribution Diagram

Power-On Sequence Diagram

The TE0803 SoM meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

The on-board voltages of the TE0803 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DC-DC converters. The on-board voltages will be powered up at three steps.

1. Low-Power Domain (LPD)
2. Programmable Logic (PL) and Full-Power Domain (FPD)
3. PS GTR transceiver and DDR memory (additionally GTH transceiver at modules with ZU5EV MPSoC)

Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance has to be asserted.

Following diagram clarifies the sequence of enabling the three power instances utilizing the DC-DC converter control signals ('Enable', 'Power-Good'), which will power-up in descending order as listed in the blocks of the diagram.

Figure 4: Power-On Sequence Utilizing DC-DC Converter Control Signals

Operation Conditions of the DC-DC Converter Control Signals

The control signals have to be asserted on the B2B connector J2, whereby some of the Power Good Signals need external pull-up resistors.

Table 16: Recommended operation conditions of DC-DC converter control signals

Core voltages and main supply voltages have to reach stable state and their "Power Good" signals have to be asserted before other voltages like bank I/O voltages (VCCOx) can be powered up.

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good" signals are high, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0803 SoM.

Voltage Monitor Circuit

The voltages 'LP_DCDC' and 'LP_0V85' are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (J2-83) to GND. Leave this pin unconnected or connect to VDD (LP_DCDC) when unused.

Figure 5: Voltage monitor circuit

Power Rails

Table 17: Power rails of the MPSoC module on accessible connectors

Bank Voltages

Table 18: Range of MPSoC module's bank voltages

B2B connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Extended grade: 0°C to +100°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers
• Mating height with standard connectors: 4mm
• PCB thickness: 1.6mm
• Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

Revision History

Hardware Revision History

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]		Ali Naseri	updated B2B connector max. current rating per pin
2017-11-13	v.19	John Hartfiel	rework B2B section
2017-10-19	v.18	John Hartfiel	Removed ES1 Note
2017-08-15	v.17	Vitali Tsiukala	Changed Signals Count in the table B2B-connectors
2017-08-07	v.14	Jan Kumann	New smaller images. New QSPI Flash MIO mapping table. Temperature information changes. Few corrections.
2017-05-17	V.4	Ali Naseri	Current TRM release.
2017-05-10	v.1	Ali Naseri	Initial document.

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