• Last modified: Mar 06, 2026


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Overview

The Trenz Electronic TEF1001 FPGA PCI Express Card integrates the AMD Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA. The TEF1001 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host system to meet the power supply requirements.

The FPGA board is designed for high system resources and intended for use in applications with high demands on system performance and throughput. To extent the board with standard DDR3 SDRAM memory module, there is a 204-pin SODIMM socket with 64-bit databus width with ECC support on the board present. High-speed data transmission is enabled by the 4 lane PCIe Gen 2 interface.

The board offers a HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard FPGA Mezzanine cards and modules. Other interface connectors found on-board include JTAG for accessing the FPGA and the on-board System Controller.

Refer to http://trenz.org/tef1001-info for current online available documentation.

Key Features

  • FPGA
    • AMD Kintex-7 FPGA 1): XC7K160T / XC7K325T / XC7K410T
    • Speed-grade 1):            -1 / -2 / -3 / -1L / -2L/ -2LE
    • Temperature Range 1): C / E / I
    • Package 3):                   FBG676 / FFG676
    • Heat sink options available 4)
  • RAM/Storage
    • 1x DDR3 SODIMM socket with ECC
    • 32 MB QSPI Flash (with XiP support) 2)
  • On Board
    • System Controller (LCMXO2-1200HC)
    • Installed cooling fan (5 V) for the FMC HPC device
    • Fan header for FPGA (12 V PWM)
    • Main DCDC - configurable via I2C
    • 11x green LEDs: 10x user / 1x status
  • Clocking
    • Programmable Clock Generator via I2C (Si5338)
    • Dedicated oscillators for FPGA and PLL
  • Interface
    • PCIe 2.0 X4 - mechanically X8 for better resilience
    • DDR3 SODIMM socket 204 pins
    • FMC HPC connector:
      • MGT/GTX: 4x lanes
      • MGT/GTX: 2x reference CLK inputs
      • IO HR:   160x SE / 80x DIFF
      • IO HR:       4x reference CLKs inputs
      • JTAG and I2C
    • JTAG connectors:
      • for the FPGA - 14x box header 2 mm
      • for the System Controller - 6x pin header (not populated)
    • I2C net header for System Controller and configurable DCDC
    • 1x reset button
    • 4x DIP switches
    • Boot mode header
  • Power
    • Single Rail (12 V) power supply
    • Power supply via PCIe 6x power connector or PCIe slot
    • Reverse polarity, over and under voltage protection for both supply options
    • Prioritisation of the ATX PCIe 6 pin power connector over the PCIe slot
    • On-board high-efficiency switch-mode DCDC converters
    • System management and power sequencing
  • Dimension
    • 106.65 mm x 167.65 mm
  • Notes

1) Available as assembly variant or upon request.
2) Other sizes/devices, which are pin/package-compatible, upon request.
3) The MGT performance differs by package:

  • FFG676s MGT performance is limited by the supply voltage of 1.0 V to 10.3125 Gb/s
  • FBG676s MGT performance is limited by the package to 6.6 Gb/s

4) Refer to Cooling Solutions for more information.

Block Diagram

 


TEF1001 block diagram

Main Components

 


TEF1001 main components
  1. AMD Kintex FPGA / Heat sink, U6
  2. DDR3 SODIMM socket, U2
  3. 256 Mbit QSPI Flash (Micron N25Q256A), U12
  4. On bottom, not visible - System Controller (LCMXO2-1200HC), U5
  5. Configurable step-down DCDC converter (LT LTM4676A), U4
  6. Fan 5 V (45 mm X 5 mm, 0.7 W, 1.06 CFM), M1
  7. ATX PCIe 6 pin 12V power connector, J5
  8. PCIe edge connector - X4 physical and X8 mechanical, J1
  9. FMC HPC connector, J2
  10. 4x pin header for PWM fan 12 V, J4
  11. 2x pin header for fan 5 V , J6
  12. Reset button, S2
  13. 4x DIP switches - 1x JTAG, 3x FMC voltage, S1
  14. 2x pin header - Boot mode, J11
  15. 1x green LED - status form SC, D11
  16. 10x green LEDs - user, connected to FPGA, D1 ... D10
  17. 14x Box header 2 mm - FPGA JTAG connector, J9
  18. 6x pin header (not populated) - JTAG for System Controller, J8
  19. 3x pin header- I2C for SC/U5 and DCDC/U4,

Initial Delivery State

Storage device name

Content

Notes

System ControllerFirmware

See TEF1001 CPLD Firmware / TEF1001 CPLD / TEF1001-REV01 CPLD for further information.

Quad SPI Flash

Not programmed


Programmable clock generatorNot programmed


Initial delivery state of programmable devices on the module

Signals, Interfaces and Pins

Connectors

Connector TypeDesignatorInterfaceIO countNotes
FMC HPCJ2MGT4x GTX (RX/TX)Bank 116
FMC HPCJ2MGT CLK2x GTX CLKBank 116
FMC HPCJ2IO48x SE / 24x DIFFBank 12
FMC HPCJ2IO CLK2x DIFFBank 13
FMC HPCJ2IO34x SE / 17x DIFFBank 13
FMC HPCJ2IO CLK2x DIFFBank 15
FMC HPCJ2IO34x SE / 17x DIFFBank 15
FMC HPCJ2IO44x SE / 22x DIFFBank 16
PCIe 2.0 X4J1MGT4x GTX (RX/TX)Bank 115
PCIe 2.0 X4J1MGT CLK1x GTX CLKBank 115
Board Connectors

Test Points

Testpoints are used since revision 03.

Test Point

Top

Bottom

Signal

Notes

TP1

x


1V8


TP2


x

3V3FMC


TP3

x


3V3FMC


TP4


x

3V3


TP5

x


3V3


TP6


x

1V


TP7


x

1V


TP8


x

12V_input_A


TP9

x


12V_input_A


TP10


x

12V


TP11

x


12V


TP12


x

12V_input_B


TP13

x


12V_input_B


TP14


x

1V8


TP15

x


PG_MGT_AVCC


TP16


x

PG_MGT_AVCC


TP17

x


MGTAVTT_FPGA


TP18


x

MGTAVTT_FPGA


TP19

x


MGTAVCC_FPGA


TP20


x

MGTAVCC_FPGA


TP21

x


MGTVCCAUX_FPGA


TP22


x

MGTVCCAUX_FPGA


TP23

x


1V5


TP24


x

1V5


TP25



-


TP26



-


TP27

x


5V


TP28


x

5V


Test Points Information

On-board Peripherals

Chip/InterfaceDesignatorConnected ToNotes

FPGA

U6
  • System Controller U5
  • FMC HPC J2
  • PCIe 2.0 X4 J1
  • Programmable Clock generator U13
  • JTAG header J9
  • Oscillator U1
  • Green user LEDs D1 to D10

System Controller

U5
  • FPGA U6
  • FMC HPC J2
  • PCIe 2.0 X4 J1
  • Programmable Clock generator U13
  • JTAG header J8
  • I2C header J10
  • Red status LED D11

See TEF1001 CPLD Firmware / TEF1001 CPLD / TEF1001-REV01 CPLD for further information.

Programmable Clock Generator

U13
  • FPGA U6
  • System Controller U5
  • Oscillator U14

Configurable DCDC step-down converter

U4
  • FPGA U6
  • System Controller U5
  • I2C header J10

Oscillator

U1
  • FPGA U6
200 MHz
OscillatorU14
  • Programmable Clock Generator U13
25 MHz
On board peripherals

Configuration and System Control Signals

Control signals represent hardware defined logic states, for final state consider the firmware and reference designs.

Control Signals and Buses

Signal Name

Connector.Pin

Direction 1)

Description

FPGA_BOOT_MODE

J11.1

IN

Jumper to select boot source, either QSPI or JTAG.

PCIE_RSTb

J1.A11

IN

Signals all power rails and the REFCLK/PCIE_CLK_C/PCIE_CLK signal have stabilized.

JTAG ( CPLD_JTAG_TMS / CPLD_JTAG_TDI / CPLD_JTAG_TDO / CPLD_JTAG_TCK )

J8.1 / J8.2 / J8.3 / J8.4

Signal dependent


JTAG ( FPGA_JTAG_TMS / FPGA_JTAG_TCK / FPGA_JTAG_TDO / FPGA_JTAG_TDI )

J9.4 / J9.6 / J9.8 / J9.10

Signal dependent


I2C ( LTM_SCL / LTM_SDA )

J10.1 / J10.3

Signal dependent


1) Direction:

    • IN: Input from the point of view of this board.

    • OUT: Output from the point of view of this board.

    • INOUT: Bidirectional signal.
    • Signal dependent: A Signal can have different functions and directions as part of a Bus.
Control signals and buses

FMC connector

Signal Name

Connector.Pin

Direction 1)

Description

FMC_TRST

J2F.D34

-

Currently not used

FMC_PRSNT_M2C_L / FMC_PRSNT

J2F.H2

IN

FMC populated status. FMC_PRSNT is inverted to FMC_PRSNT_M2C_L

FMC_PG_C2M

J2F.D1

-

Currently not used

FMC_PG_M2C

J2F.F1

-

Currently not used

I2C ( FMC_SCL / FMC_SDA )

J2F.C30 / J2F.C31

Signal dependent


JTAG ( FMC_TCK / FMC_TMS / FMC_TDI / FMC_TDO)

Signal dependent

J2F.D29 / J2F.D33 / J2F.D30 / J2F.D31


1) Direction:

    • IN: Input from the point of view of this board.

    • OUT: Output from the point of view of this board.

    • INOUT: Bidirectional signal.
    • Signal dependent: A Signal can have different functions and directions as part of a Bus.
FMC connector

Button

Button

Signal

Logic state

Function

Low

high

S2

BUTTON

pressed

unpressed 

Reset
Button

DIP switches

DIP switch

Signal

DIP switch name

Description


S1

JTAG_EN

S1A

Enable JTAG to the System Controller.

SIG0_FMC_VADJ_CTRL

S1B

Set the voltage of U7 / Power rail FMC_VADJ.

S1DS1CS1BVoltage
OFFOFFOFF3.3V
OFFOFFON2.5V
OFFONOFF1.8V
OFFONON1.5V
ONOFFON1.2V

SIG1_FMC_VADJ_CTRL

S1C

SIG2_FMC_VADJ_CTRL

S1D

DIP switches

Power and Power-On Sequence


Power Rails

Power Rail Name / Schematic Name

Connector.Pin

Direction 1)

Notes

12V_input_A

J5.1 / J5.2 / J5.3

IN

Prior card supply

12V_input_B

J1.B1 / J1.B2 / J1.B3 / J1.A2 / J1.A3

IN

Secondary card supply

1.8V

J9.2

OUT

External IO supply

3.3V

J8.6

OUT

External IO supply

12V

J2G.C35 / J2G.C37

OUT

FMC supply.

3.3V

J2G.D32

OUT

FMC supply.

3.3VFMC

J2G.D36 / J2G.D38 / J2G.D40 / J2G.D39

OUT

FMC supply.

VOI_B_FMC

J2G.J39 / J2G.K40

IN

External FMC IO supply output for FPGA bank 16.

FMC_VADJ

J2G.H40 / J2G.G39 / J2G.F40 / J2G.E39

OUT

FMC supply.

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Module power rails.

Recommended Power up Sequencing


SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
0---Configuration signal setup.See Configuration and System Control Signals.
1

12V_input_A

12V_input_B

12 V (± 10 %)

12 V (± 10 %)

-

-

Primary Power supply, PCIe 6 Pin Power Connector. 

Secondary Power supply, PCIe Slot. 

The boards Power-up Sequence is handled by its System Controller.

Baseboard Design Hints

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

Power Rail Name/ Schematic NameDescriptionMinMaxUnit

12V_input_A

Prior card supply

-0.320V

12V_input_B

Secondary card supply

-0.320V
VOI_B_FMCExternal FMC IO supply output for FPGA bank 16.-0.53.6V
Absolute maximum ratings

*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

  • Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
  • Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
  • Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

  • Customer SoC design. The allowed main SoC temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
  • Cooling solution, active and or passive cooling.
  • Climate or environmental conditions besides ambient temperature range.
  • Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.

Classification of the module can be looked up here: Article Number Information i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).

ParameterMinMaxUnitsReference Document

12V_input_A

10.813.2VRefer to TEF1001 schematic.

12V_input_B

10.813.2VRefer to TEF1001 schematic.
VOI_B_FMC1.143.465VRefer to FPGA data-sheet.
Recommended operating conditions.


Physical Dimensions

  • Module size: 106.65 mm × 167.65 mm. Please download the assembly diagram for exact numbers.

  • PCB thickness: 1.66 mm ± 10 %.


 


Physical Dimension

Currently Offered Variants 

Trenz shop TEF1001 overview page*
English pageGerman page

*)  Module article name encoding table: AMD 7 Series Spartan Artix and Kintex based modules

Trenz Electronic Shop Overview

Revision History

Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by a dash.

 


Board hardware revision number.


Date

Revision

Changes

Documentation Link

2024-12

REV03

  1. Removed the 4V power domain.
  2. Replaced U3 LTM4676AEY with the MPM3650CGQW regulator to manage the 1.5V
    power domain.
  3. Replaced U20 EN6347QI with the MPM3650CGQW regulator to manage the 1.8V power
    domain. The input supply switched from 4V to 12V.
  4. Replaced U15 EN6347QI with the MPM3650CGQW regulator to manage the 3V3FMC
    power domain. The input supply switched from 4V to 12V.
  5. Replaced U7 EN5365QI with the MIC24046YFL regulator to manage the FMC_VADJ
    power domain. The input supply switched from 4V to 12V. Added U26 and U27
    #VC1T45DW-7 transceivers. FMC_VADJ = 1.25V, 1.0V - 0.7V are not supported.
  6. Updated U17 and U18 TPS74401RGW BIAS supply voltage from 4V to 3.3V
  7. Updated U16 TPS51206DSQ VDD supply voltage from 4V to 3.3V.
  8. Connected U22 SN74AVC4T774RSVR pins B1 and B3 to GND to prevent floating input
    signals.
  9. Updated the BRx connection for board revision 03, Bank 14.
  10. CPLD Signal and Pinning Updates:
    1. PT12D (Pin 85): renamed net LTM_1V5_4V_IO0 to PG_1V5.
    2. PT15B (Pin 83): removed net LTM_1V5_4V_IO1 (N/A).
    3. PR2A (Pin 75): removed net LTM_4V_RUN (N/A).
    4. PR2B (Pin 74): renamed net LTM_1V5_RUN to EN_1V5.
    5. PR3A (Pin 71): renamed VID0_FMC_VADJ_CTRL to SIG0_FMC_VADJ_CTRL.
    6. PR5C (Pin 63): renamed VID1_FMC_VADJ_CTRL to SIG1_FMC_VADJ_CTRL.
    7. PR5D (Pin 62): renamed VID2_FMC_VADJ_CTRL to SIG2_FMC_VADJ_CTRL.
    8. PR5A (Pin 64): reassigned LTM2_ALERT (N/A) to VOSET0_FMC_VADJ_A.
    9. PR9B (Pin 57): reassigned VID2_FMC_VADJ to VOSET0_FMC_VADJ_DIR.
    10. PR9C (Pin 54): reassigned VID1_FMC_VADJ to VOSET1_FMC_VADJ_A.
    11. PR9D (Pin 53): reassigned VID0_FMC_VADJ to VOSET1_FMC_VADJ_DIR.
  11. R33 resistor is not populated
  12. Added support for FPGA JTAG boot mode: U6 M2_0 is connected to CPLD PT15A (pin84) via transceiver U28. Added Jumper J11 for boot mode selection.
  13. Replaced T1, T2, T5 and T6 transistors SiS444DN to SiS4604LDN.
  14. PCIE_PRSNTb signal is disconnected from PCIE edge connector J1 pin B48 and connected to pin J1 B31 for PCIE x4 lane identifacation
  15. R31 is changed to pull-down resistor.
  16. All capacitors 100μF 10V X5R 20% 3216 (1206) changed to 100μF 6,3V X5R 20% 3216 (1206) (BOM optimisation)
  17. Changed resistor divider values R65, R71 and R77 (BOM optimisation)

REV03

PCN

2018-12

REV02

  1. Added capacitors C87 and C88, each 4.7μF.
  2. Increased the value of capacitor C154 from 27pF to 33pF.
  3. Power Input and Protection Enhancements:
    1. Routed 12V input from the PCIe edge connector.
    2. Added input power protection circuits for both ATX 12V and PCIe edge connector,
      involving components U23 with T1, T2 and U24 with T5, T6, along with associated resistors
      and capacitors.
    3. Introduced a power priority switch (T3) to prioritize ATX power.
  4. Added switch S1 for selecting FMC_VADJ value and enabling JTAG (JTAG_EN).
  5. Added transistor T4 and resistors for reading the FMC_PRSNT_M2C signal.
  6. Added U25 and associated capacitors to support the FMC fan.
  7. Added screws for the bracket installation.
  8. Added 10 FPGA LEDs (D1-D10) controlled via level shifters (U11, U21, U22).

9. Replaced the FAN model F455B-05MD (EOL) with F455B-05LD.

REV02

PCN
PCN

-

REV01

Initial release

REV01

Hardware Revision History

Document Change History

DateRevisionAuthorsDescription

v.43

Kilian Jahn

  • Updated to TRM Template 4.3.
  • Updated to Hardware Revision 03

2018-12-11

v.42

 Pedram Babakhani

  • Update picture
2018-10-24v.41Guillermo Herrera
  • Initial document

--

all

Pedram Babakhani , Ali Naseri , GH , John Hartfiel , Kilian Jahn

  • --
Document change history

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Product Disclaimer

Products (incl. Software and Firmware) are exclusively designed, manufactured, and distributed for industrial applications. They are not intended, authorized, or certified for use in critical safety applications, medical devices, aerospace, nuclear, life-support, traffic-control, military, or other environments where malfunction or failure could result in personal injury, death, or significant property or environmental damage.

Trenz Electronic GmbH (“Manufacturer”) excludes any liability for inappropriate use in such contexts. The Customer bears all responsibility for verifying suitability and compliance with applicable regulations when deploying in any critical-use scenario. The Customer also agrees to indemnify and hold harmless the Manufacturer from any third-party claims or liabilities arising from such use.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.



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