TEBF0818 TRM

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Overview

The Trenz Electronic TEBF0818 board is a carrier for Trenz TE0813, TE0817 and TE0818 SoMs, which are equipped with AMD Zynq Ultrascale+ MPSoCs.

It exposes the SoMs B2B connectors to a whole range of basic PC, consumer and development IO connectors. These connectors provide the grounds for testing, evaluation and development purposes.

The carrier board is designed for the Mini-ITX Form Factor, which makes it capable to be fitted into a PC enclosure. On the PC enclosure's rear and front panel, interfaces and connectors are accessible. For the front panel are Intel-PC compatible headers available.

Refer to https://trenz.org/tebf0818-info for current online available documentation.

Key Features

On Board
- 2x System Controller for periphery and SoM management
- 10/100/1000 BASE-T/X Ethernet PHY
- USB 3.0 PHY with VBUS control
- USB 2.0 PHY
- SDIO port switch
- 2x adapters TE0790 to convert USB 2.0 (Mini USB Type B) to JTAG/UART and SPI/I2C/IO
- CAN bus transceiver
- 2x BUS transceiver for IO
- 2x I2C switches
- Clocking:
  - Programmable Clock Generator
  - Clock fanout buffer for PCIe
  - Dedicated oscillator for SoM
  - Dedicated oscillators for each PHY
- LEDs:
  - 2x for RJ45 status signalling
  - 4x for SFP+ cages
  - 2x 2 for system controller status
  - 1x USB 3.0 status
- Options ¹⁾:
  - Programmable oscillator
  - Controller for 5 V FMC fan
  - Smart power switch for 12 V fan
Storage ²⁾
- e.MMC 8 GB
- 3x EEPROMs with 1536 bit storage and 48 bit MAC address
- 2x EEPROMs with 2 kbit storage
Interface
- SoM socket - Trenz 5.2 x 7.6 4x B2B connector (Samtec ADF6)
- Basic PC Standards:
  - Intel HD Audio header
  - Intel front panel IO header
  - PC beeper header - 4 pin
  - 3x Fans - 4-Wire: 2x 12 V and 1x 5 V
  - Power and Reset Button
  - 2x 4 DIP switches for configuration
  - 2x USB 3.0 A and 1x RJ45 Ethernet - stacked, back panel
- Consumer Standards:
  - USB 3.0 header
  - PCIe 2.0 x1 slot - physical PCIe x16
  - DisplayPort
  - SATA socket
  - MicroSD Card socket
  - MM Card socket
- Industrial Standards:
  - 2x SFP+ cages
  - Samtec FireFly connector
  - Samtec FireFly loopback connector
  - 2x CAN bus header
- Development Standards:
  - FMC HPC connector
  - I2C header for:
    - FireFly connector I2C
    - Programmable PLL on SoM
  - Pmod header for :
    - 2x I2C
    - 1x for 8x IO
  - JTAG/UART headers for TE790 adapters:
    - 1x SoM
    - 1x shared between System Controllers and FMC connector
  - JTAG / PJTAG header for ARM on SoM
  - SMA connector for clock signals as:
    - output from Clock Generator
    - input to SoM
Power
- 24x pin ATX power connector
- Barrel jack - 2.1 mm, for single power adapter supply
- Reverse polarity, over and under voltage protection for both supply options
- Prioritisation of the ATX power connector over the barrel jack connector
- Controlling and monitoring of SoM voltage levels
- Backup battery holder - CR1220 / 3V
Dimension
- 170 mm x 170 mm / Mini-ITX form factor
Notes

¹⁾ Available as assembly variant or upon request.
²⁾ Pin/Package-compatible sizes upon request.

Block Diagram

TEBF0818 block diagram

Main Components

TEBF0818 main components

ATX-24 power supply connector, J20
Barrel power Jack 2.1mm, J25
Battery holder for CR1220, B1
Intel front panel IO header, J10
Intel HD Audio header, J9
PC beeper header, J23
Power Button, S1
Reset Button, S2
4x DIP switches, S4, S5
Fan connector 5 V 4-Wire PWM for FMC, J19
Fan connector 12 V 4-Wire PWM, J26, J35
2x USB 3.0 A and RJ45 Ethernet (stacked), J7
USB 3.0 header, J8
PCIe x1 connector - physical PCIe X16, J11
DisplayPort connector, J13
SATA header, J31
MicroSD Card socket (on bottom), J16
e.MMC Card socket, J27
2x SFP+ cages, J14
FMC HPC connector, J5
Samtec FireFly connector, J6/J15
Samtec FireFly loopback connector, J21/J22
I2C header for FireFly, J34
I2C header for programmable SoM PLL, J17
Pmod I2C header, P1, P3
Pmod 8x IO connector, P2
CAN bus header, J29, J24
TE0790 adapter. JTAG/IO header for SoM, J12
TE0790. JTAG/IO header for System Controller, J28
JTAG / PJTAG header for ARM on SoM, J30
SMA connector - CLK output from CLK generator, J32
SMA connector - CLK input to SoM, J33
B2B connectors (Samtec SS5), J1, J2, J3, J4
Primary System Controller, U17
Secondary System Controller, U39
e.MMC, U2
Ethernet PHY, U12
USB 3.0 PHY, U4
USB 2.0 PHY, U9
HD Audio, U3
Fan controller, U54
I2C switch, U16 - on bottom, U27 - concealed by TE0790
EEPROM, U5, U24
EEPROM with MAC, U36, U41, U42
IO Expander, U38 - PCIe and FMC connector
IO Expander, U44 - SFP+ cages
Programmable Clock Generator, U35

Initial Delivery State

Storage device name	Designator	Content	Notes
System Controller	U17 / U39	Firmware	Refer to TEBF0818 CPLD Firmware / TEBF0818 CPLD for more information.
e.MMC	U2	Not programmed
Programmable Clock Generator	U35	Not programmed
Programmable Oscillator	U45	Not programmed	Device is optional / Carrier variant dependent.
EEPROM	U5 / U24	Not programmed
EEPROM with MAC	U36 / U41 / U42	Not programmed	MAC is burned-in by the manufacturer.
TE0790 adapter for SoM	J12	Firmware	Refer to TE0790 TRM Documentation for more information.
TE0790 adapter for System Controller	J28	Firmware	Refer to TE0790 TRM Documentation for more information.

Initial delivery state of programmable devices on the module

Signals, Interfaces and Pins

Connectors

Connector Type	Designator	Interface	IO count	Notes
B2B	J1	MGT FMC	10x MGT (RX/TX)
B2B	J1	IO	48x SE / 24x DIFF
B2B	J2 / J3	CLK loopback	1x DIFF	CLK loop of B230_CLK1 and CLK7
B2B	J2	CLK out	1x DIFF	Oscillator U23 (B505_CLK1)
B2B	J2	CLK out	1x DIFF	PCIe inferred CLK B505_CLK0
B2B	J2	CLK in	1x DIFF	CLK8 - Input to CLK generator U35
B2B	J2	CLK in	1x DIFF	CLK0 - Input to PCIe CLK fanout U56.
B2B	J2	MGT FireFly	4x MGT (RX/TX)
B2B	J2	MGT DisplayPort	1x MGT
B2B	J2	MGT SATA	1x MGT (RX/TX)
B2B	J2	MGT USB 3.0	1x MGT (RX/TX)
B2B	J2	MGT PCIe 2.0	1x MGT (RX/TX)
B2B	J3	IO	22x SE / 11x DIFF
B2B	J3	GPIO	10x SE	Connection to the Primary System Controller U17.
B2B	J3	GPIO	8x SE	Connection to the Secondary System Controller U39.
B2B	J3	CLK out	1x DIFF	Optional CLK
B2B	J3	CLK out	1x DIFF	SMA J33
B2B	J3	MGT FMC CLK	2x DIFF
B2B	J3	HD Audio	4x SE	Data, bit and frame CLK
B2B	J3B	e.MMC	11x SE
B2B	J3	MIO	4x SE	Connection to the Primary System Controller U17.
B2B	J3	MIO	15x SE	Connection to the Secondary System Controller U39.
B2B	J3	SD IO	7x SE
B2B	J3	USB ULPI	12x SE
B2B	J3	ETH RGMII	12x SE
B2B	J3	ETH MDIO	2x SE
B2B	J4	IO	96x SE / 48x DIFF
B2B	J4	IO	3x SE	IO between SC U17 and SoM.
B2B	J4	IO	4x SE	Pmod P2 to SoM.
microSD card	J16	SD IO	7x SE
MMC SD	J27	SD IO	8x SE
RJ45	J7	ETH MDI	4x DIFF
SFP+	J14A / J14B	MGT SFP+	2x MGT (RX/TX)
FireFly	J6 / J15	MGT FireFly	2x MGT (RX/TX)
FireFly	J21 / 22	MGT FireFly loopback	4x DIFF
DisplayPort	J13	MGT DisplayPort	1x MGT
SATA	J31	MGT SATA	1x MGT (RX/TX)
USB 3.0 type A	J	USB 3.0	2x 3 DIFF
USB 3.0 box header	J8	USB 3.0	6x DIFF
PCIe edge connector	J	MGT PCIe 2.0	1x MGT (RX/TX)
FMC HPC	J5	MGT FMC	10x MGT (RX/TX)
FMC HPC	J5	MGT CLK FMC	2x DIFF
FMC HPC	J5	IO	164x SE / 82x SE
FMC HPC	J5	IO CLK	2x DIFF
Micro USB 2.0 type b / TE0790	J12	USB 2.0	1x DIFF
Micro USB 2.0 type b / TE0790	J28	USB 2.0	1x DIFF
Intel HD Audio header	J9	HD Audio	5x SE
SMA	J32	IO CLK out	1x SE	CLK output from Clock Generator.
SMA	J33	IO CLK in	1x SE	SoM CLK input
Pmod header	P2	IO	8x SE

Board Connectors

Test Points

Test Point	Top	Bottom	Signal	Notes
TP1	x		USB3_ID	USB 3.0
TP2		x	PSBATT
TP3		x	FMC_VADJ
TP4		x	VCC_MOD
TP5		x	3.3V_PCI
TP6		x	5V
TP7		x	1.8V
TP8		x	3.3V_PER
TP9		x	1.2V
TP10		x	3V3SB
TP11		x	12V_input_A
TP12	x		AVDD_CORE / U4C.VDD_EFUSE
TP13		x	LDO_3.3V
TP14		x	PLL_FDEC
TP15		x	PLL_3V3
TP16		x	PLL_FINC
TP17			-	Not used
TP18		x	DP_TX_PWR
TP19		x	DP_TX_HPD
TP20 ... TP27			-	Not used
TP28		x	GND
TP29		x	GND
TP30		x	GND
TP31		x	GND
TP32		x	GND
TP33		x	USB0_ID	USB 2.0

Test Points Information

On-board Peripherals

Chip/Interface	Designator	Connected to	Notes
System Controller	U17	ETH PHY U12 USB 3.0 PHY U4 USB 2.0 PHY U9 Fan 2 J35 Pmod P2 I2C CAN Transceiver U30 Bus transceiver U32 System controller U39 DIP switch S5 USB 3.0 Plug J7 MMC card socket J27 XMOD/TE0790 J28 20x Box/JTAG header J30 B2B J3 SFP Status LEDs D1/D8/D9/D10 ETH Status LEDs Status LEDs D4/D5 FMC J5	For further information refer to TEBF0818 CPLD Firmware / TEBF0818 CPLD.
System Controller	U39	CLK U25 HD Audio U3 SDIO switch U15 MicroSD card J16 MMC card J27 Fan 1 J26 and Fan FMC J19 Beeper J23 I2C DIP switches S4 and S5 Button S1 and S2 XMOD/TE0790 J28 XMOD/TE0790 J12 Front panel IO J10 B2B J2 and J3 Status LEDs D6/D7 FMC J5	For further information refer to TEBF0818 CPLD Firmware / TEBF0818 CPLD.
e.MMC	U2	B2B J3
ETH PHY	U12	System controller U17 CLK U13 RJ45 connector J7 B2B J3
USB 3.0 PHY	U4	USB 2.0 PHY U9 Crystal Y1 I2C System controller U17 USB VBUS controller U14/U21 USB Status LED D17 USB 3.0 connector J7 and header J8
USB 2.0 PHY	U9	USB 3.0 PHY U4 CLK U10 System controller U17 B2B J3
HD Audio	U3	I2C System controller U39 HD audio header J9 B2B J3
FMC connector	J5	I2C System controller U17 and U39 Clock generator U35 B2B J1/J3/J4
SDIO switch	U15	System controller U39 MicroSD card socket J16 MM card socket J27
Fan controller	U54	FAN FMC J19 I2C
I2C switch	U16	I2C
I2C switch	U27	I2C
EEPROM	U5	I2C	Intended for USB 3.0 PHY.
EEPROM	U24	I2C
EEPROM with MAC	U36	I2C
EEPROM with MAC	U41	I2C
EEPROM with MAC	U42	I2C
Pmod	P1	I2C
Pmod	P2	System controller U17 Level shifter U33
Pmod	P3	I2C
IO Expander	U38	I2C FMC HPC connector J5 PCIe x1 J11
IO Expander	U44	I2C SFP connector J14
XMOD / TE0790	J12	System controller U39 B2B J2	See TE0790 TRM Documentation for further information.
XMOD / TE0790	J28	System controller U17 System controller U39	See TE0790 TRM Documentation for further information.
Bus transceiver	U32	System controller U17 B2B J4
Bus transceiver	U33	Pmod P2 B2B J1/J4
Clock Generator	U35	B2B J2 System controller U17 FMC HPC connector J5 SMA CLK out J32
Clock Fanout	U56	PCIe x1 J11 B2B J2
Oscillator programmable ¹⁾	U45	B2B J3	Optional
Oscillator CRY	Y1	USB 3.0 PHY U4	26 MHz
Oscillator	U7	Clock generator U35	25 MHz
Oscillator	U23	B2B J2	150 MHz
Oscillator	U25	System controller U39	24.576 MHz for HD Audio
Oscillator	U13	ETH PHY U12	25 MHz
Oscillator	U10	USB 2.0 PHY U9	52 MHz

¹⁾ Default assembly option: not fitted

On board peripherals

Configuration and System Control Signals

Signal Name	Connector Type	Connector.Pin	Direction ¹⁾	Description
ERR_STATUS	B2B	J2A.A34	IN	SoM PS Error Status ^{2) 3)}
ERR_OUT	B2B	J2A.A31	IN	SoM PS Error Out ^{2) 3)}
SRST_B	B2B	J2B.B33	OUT	SoM reset signal ^{2) 3)}
INIT_B	B2B	J2B.B34	IN	FPGA initialisation pin or configuration error signal ^{2) 3)}
PROG_B	B2B	J2B.B30	OUT	Reset for configuration logic ^{2) 3)}
PUDC_B	B2B	J2B.D38	OUT	Set the state of internal pull-up resistors for selected IO pins after power-up and during configuration ^{2) 3)}
MR	B2B	J2B.C31	OUT	SoM PS Power Reset ^{2) 3)}
DONE	B2B	J2B.B46	INOUT	Programming System initialisation finished signal ^{2) 3)}
POR_OVERRIDE	B2B	J1A.A45	OUT	POR delay override ³⁾
MODE0 / MODE1 / MODE2 / MODE3	B2B	J2B.C47 / J2B.C46 / J2B.C45 / J2B.C44	OUT	SoM Boot Mode ^{2) 3)}
EN_LPD	B2B	J2B.B42	OUT	Enable the Low Power Domain voltage ²⁾
LP_GOOD	B2B	J2A.A35	IN	Signals the state of Low Power Domain voltage ²⁾
EN_FPD	B2B	J2B.B38	OUT	Enable the Full Power Domain voltage ²⁾
PG_FPD	B2B	J2B.B41	IN	Signals the state of Full Power Domain voltage ²⁾
EN_PL	B2B	J2B.C35	OUT	Enable the Programmable Logic voltage ²⁾
PG_PL	B2B	J2B.B37	IN	Signals the state of Programmable Logic voltage ²⁾
EN_PSGT	B2B	J2A.A41	OUT	Enable the Programming System Gigabit Transceiver voltage ²⁾
PG_PSGT	B2B	J2B.B29	IN	Signals the state of the Programming System Gigabit Transceiver voltage ²⁾
EN_DDR	B2B	J2B.B47	OUT	Enable the DDR voltage ²⁾
PG_DDR	B2B	J2B.B45	IN	Signals the state of DDR voltage ²⁾
EN_GT_L	B2B	J2B.C30	OUT	Enable the SoMs left Gigabit Transceiver voltage ²⁾
PG_GT_L	B2B	J2A.A40	IN	Signals the state of left Gigabit Transceiver voltage ²⁾
EN_GT_R	B2B	J2B.C36	OUT	Enable the right Gigabit Transceiver voltage ²⁾
PG_GT_R	B2B	J2B.D33	IN	Signals the state of right Gigabit Transceiver voltage ²⁾
EN_PLL_PWR	B2B	J2B.D29	OUT	Enable the PLL voltage ²⁾
PG_PLL_1V8	B2B	J2A.A30	IN	Signals the state of the SoM PLL voltage ²⁾
PLL_SEL0	B2B	J2B.C32	OUT	SoM PLL clock selection ²⁾
PLL_SEL1	B2B	J2B.D32	OUT	SoM PLL clock selection ²⁾
PLL_FINC	B2B	J2B.D30	OUT	SoM PLL frequency incrementation ²⁾
PLL_FDEC	B2B	J2B.C37	OUT	SoM PLL frequency decrementation ²⁾
PLL_LOLn	B2B	J2B.D31	IN	SoM loss of lock status ²⁾
PLL_RST	B2B	J2B.C33	OUT	SoM PLL reset ²⁾
PUDC_B	DIP switch	S4A	IN	Set the state of internal pull-up resistors for selected IO pins after power-up and during configuration ^{2) 3)}
-	DIP switch	S4B	-	Not connected
JTAGENB	DIP switch	S4C	IN	Select JTAG target ^{2) 3)}
12V / 5V_EN / U18.EN	DIP switch	S4D	IN	Define boot behaviour of the 5 V rail. Power for FMC, USB VBUS and Display Port are enabled during boot, or after generating the 5V_EN signal.
SC2_SW1	DIP switch	S5A	IN	Set SoM Boot Mode ^{2) 3)}
SC2_SW2	DIP switch	S5B	IN	Set SoM Boot Mode ^{2) 3)}
SC2_SW3	DIP switch	S5C	IN	User definable.
SC2_SW4	DIP switch	S5D	IN	FMC_VADJ voltage selection ²⁾
PWR_BTN	Button	S1	IN	Power on the carrier and SoM ²⁾
RST_BTN	Button	S2	IN	Reset the carrier and SoM ²⁾
PWR_OK	ATX 24x pin	J20.8	IN	The power supply unit signals that it has passed its internal self-tests and the outputs have stabilised.
PS_ON_N	ATX 24x pin	J20.16	OUT	Turn the power supply unit on/off. Inverted signal logic.
HD_LED_P / HD_LED_N	Front IO panel	J10.1 / J10.3	OUT	Hard drive activity LED
PWRLED_P / PWRLED_N	Front IO panel	J10.2 / J10.4	OUT	Power / Sleep / Message waiting LED
RST_BTN	Front IO panel	J10.7	IN	Reset button
PWR_BTN	Front IO panel	J10.6	IN	Power button
HDA_SENSE	HD Audio IO panel	J9.7	IN	Audio jack detection sense line
JTAG( TCK / TDI / TDO / TMS)	B2B	J2.120 /J2.122 / J2.124 / J2.126	Signal dependent	JTAG for SoM
JTAG( TCK / TDO / TDI / TMS)	Adapter / TE0790	J12.4 / J12.8 / J12.10 / J12.12	Signal dependent	JTAG for SoM
JTAG( C_TCK / C_TDO / C_TDI / C_TMS)	Adapter / TE0790	J28.4 / J28.8 / J28.10 / J28.12	Signal dependent	JTAG for System Controllers and FMC
JTAG( FMC_TCK / FMC_TMS / FMC_TDI / FMC_TDO )	FMC HPC	J5F.D29 / J5F.D33 / J5F.D30 / J5F.D31	Signal dependent	JTAG for FMC connector
CON_NTRST	Box header	J30.3	IN	JTAG reset ^{2) 4)}
CON_RTCK	Box header	J30.11	OUT	Return Test Clock pin, echos the test clock signal ^{2) 4)}
CON_sRST	Box header	J30.15	IN	SoC ARM Core reset ^{2) 4)}
JTAG( CON_TDI / CON_TMS / CON_TCK / CON_TDO )	Box header	J30.5 / J30.7 / J30.9 / J30.13	Signal dependent	Named con_JTAG in schematic and PJTAG in firmware description. JTAG for SoM ARM core. ^{2) 4)}
MIO26 / MIO27 / MIO28 / MIO29	B2B	J3A.B35 / J3A.A35 / J3A.B36 / J3A.A36	Signal dependent	Named con_JTAG in schematic and PJTAG in firmware description. JTAG for SoM ARM core. ^{2) 4)}
I2C( PLL_SCL / PLL_SDA )	B2B	J2A.A36 / J2A.A37	Signal dependent	I2C for SoM PLL
I2C( PLL_SCL / PLL_SDA )	Box header	J17.3 / J17.7	Signal dependent	I2C for SoM PLL
I2C( I2C_SCL / I2C_SDA )	B2B	J3A.B40 / J3A.A40	Signal dependent
I2C( PMOD_SCL / PMOD_SDA )	Pmod header P1	P1.3 and P1.9 / P1.4 and P1.10	Signal dependent
I2C( EXT_SCL / EXT_SDA )	Pmod header P3	P3.3 and P3.9 / P3.4 and P3.10	Signal dependent
I2C( FFA_SDA / FFA_SCL )	Pin header	J34.1 / J34.3 J15.7 / J15.8	Signal dependent	I2C Firefly
I2C( SFP1_SDA / SFP1_SCL )	SFP+	J14.T4 / J14.T5	Signal dependent	I2C SFP+ cage 1 / J14A
I2C( SFP2_SDA / SFP2_SCL )	SFP+	J14.L4 / J14.L5	Signal dependent	I2C SFP+ cage 2 / J14B
I2C( FMC_SCL / FMC_SDA )	FMC HPC	J5F.C30 / J5F.C31	Signal dependent	I2C for FMC

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
- INOUT: Bidirectional signal.
- Signal dependent: A Signal can have different functions and directions as part of a Bus.

²⁾ See TEBF0818 CPLD Firmware / TEBF0818 CPLD for further information.
³⁾ See AMD UG1085 for additional information.
⁴⁾ See ARM JTAG 20 for additional information.

Controller signal.

Power and Power-On Sequence

Power Rails

Power Rail Name / Schematic Name	Connector.Pin	Direction ¹⁾	Notes
12V_input_A	J20.10 / J20.11	IN	Carrier powered via ATX supply.
5VSB	J20.9	IN	Alternative input for U43.
12V_input_B	J25.1	IN	Carrier powered via barrel jack (2.1 mm).
VCC_MOD	J1B.C56 / J1B.C57 / J1B.C58 / J1B.C59 / J1B.C60 / J1B.D56 / J1B.D57 / J1B.D58 / J1B.D59 / J1B.D60 J2A.B50 / J2A.B51 / J2A.B52 / J2A.B57 / J2A.B58 / J2A.B59 / J2A.B60 J2B.D50 / J2B.D51 / J2B.D52 / J2B.D57 / J2B.D58 / J2B.D59 / J2B.D60 J3A.A59 / J3A.A60 / J3A.B59 / J3A.B60 J3B.C59 / J3B.C60 / J3B.D59 / J3B.D60	OUT	SoM supply
FMC_VADJ	J1A.A32 / J1A.A33 J3B.C7 / J3B.C8 / J3B.D8 / J3B.D9 J4A.B21 / J4A.B39 / J4B.C21 / J4B.D39 J5G.H40 / J5G.G39 / J5G.F40 / J5G.E39	OUT	SoM IO supply
3V3SB	J1A.A54 / J1A.A55 / J1A.B55 / J1A.B56	OUT	SoM auxiliary supply
VBATT ²⁾	B1	IN	Supplied by battery.
PSBATT ²⁾	J2D.D37	OUT	Backup supply to SoM.
PLL_3V3	J3A.A55	OUT	Supplied by 3V3SB via filter.
VREF66 / VREF_A_M2C	J1A.A41 / J5G.H1	OUT / IN	SoM IO supply, supplied via FMC.
VREF64 / VREF_A_M2C	J4A.B30 / J5G.H1	OUT / IN	SoM IO supply, supplied via FMC.
VREF65 / VREF_A_M2C	J4B.C30 / J5G.H1	OUT / IN	SoM IO supply, supplied via FMC.
PL_1V8	J1B.C32 / J1B.C33 / J1B.D33 / J1B.D34	IN	Not used
PS_1V8	J2B.C34 / J2B.D34 J3A.A56 / J3A.B56 / J3B.C56 / J3B.D56	IN	Not used
DDR_1V2	J2B.D47	IN	Not used

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ PSBATT is the LDO regulated output of VBATT.

Module power rails.

Recommended Power up Sequencing

Sequence

Net name

Recommended Voltage Range

Pull-up/down

Description

Notes

0

-

Configuration signal setup.

See Configuration and System Control Signals.

1

12V_input_A

12V_input_B

5VSB

12 V (± 5 %)

5 V (± 10 %)

-

Main Power supply.

Carrier power supply.

Either ATX (Input A) or power jack (Input B).

ATX 5 V supply is optional.

2

PWR_BTN

-

Power button S1

Baseboard Design Hints

Board to Board Connectors

5.2 x 7.6 cm UltraSoM+ modules use four Samtec AcceleRate HD High-Density Slim Body Arrays on bottom side.

4x ADM6-60-01.5-L-4-2 (legacy) or ADM6-60-01.5-L-4-0 (240 pins, 60 per row)
- Mates with ADF6-60-03.5-L-4-2 (legacy) or ADF6-60-03.5-L-4-0

5.2 x 7.6 cm UltraSoM+ carrier use four Samtec AcceleRate HD High-Density Slim Body Arrays on top side.

4x ADF6-60-03.5-L-4-2 (legacy) or ADF6-60-03.5-L-4-0 (240 pins, 60 per row)
- Mates with ADM6-60-01.5-L-4-0 (legacy) or ADM6-60-01.5-L-4-2

Features

Board-to-Board connector 240-pins, 60 contacts per row
Pitch: 0.025" (0.635 mm)
Data Rate:
- ADM6-XX-XX.X-X-X-2: 56 Gbps
- ADM6-XX-XX.X-X-X-0: 64 Gbps
Mates with: ADM6/APF6
Insulator Material: Black LCP
Contact Material: Copper Alloy
Plating: Au or Sn over 50 µ" (1.27 µm) N
Operating Temperature Range: -55 ºC to +125 ºC
Lead-Free solderable: Yes
RoHS Compliant: Yes

Connector Stacking height

When using the standard type on baseboard and module, the mating height is 5 mm. Other mating heights are possible by using connectors with a different height:

Order number	REF number	Samtec Number	Type	Contribution to stacking height	Comment
30095	REF-30095	ADM6-60-01.5-L-4-2	Module connector	1.5 mm	Standard connector used on modules (legacy)
-	-	ADM6-60-01.5-L-4-0	Module connector	1.5 mm	Alternative connector
31137	REF-31137	ADF6-60-03.5-L-4-2	Baseboard connector	3.5 mm	Standard connector used on carrier (legacy)
-	-	ADF6-60-03.5-L-4-0	Baseboard connector	3.5 mm	Alternative connector

Connectors.

Connector Speed Ratings

The AcceleRate HD High-Density connector speed rating depends on the stacking height; please see the following table:

Connector	Stacking height	Speed rating
ADM6-XX-XX.X-X-X-2	5 mm	56 Gbps
ADM6-XX-XX.X-X-X-0	5 mm	64 Gbps

Speed rating.

Current Rating

Current rating of Samtec AcceleRate HD High-Density B2B connectors is 1.34 A per pin (4 pins powered).

Connector Mechanical Ratings

Shock: 100G, 6 ms Sine
Vibration: 7.5G random, 2 hours per axis, 3 axes total

Manufacturer Documentation

	File	Modified
	PDF File 20200225_hsc_adm6-xx-01p5-xxx-4-a_adf6-xx-03p5-xxx-4-a.pdf	Jan 10, 2022 by Martin Rohrmüller
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	PDF File adf6.pdf	Jan 10, 2022 by Martin Rohrmüller
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	PDF File ADF6-XXX-XX.X-XXX-X-X-X-FOOTPRINT.PDF	Jan 10, 2022 by Martin Rohrmüller
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	PDF File adf6-xxx-xx.x-xxx-x-x-x-xr-mkt.pdf	Jan 10, 2022 by Martin Rohrmüller
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	PDF File adx6 mated document.pdf	Jan 10, 2022 by Martin Rohrmüller
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	PDF File Updated - 20200225_hsc_adm6-xx-01p5-xxx-4-a_adf6-xx-03p5-xxx-4-a.pdf	Jun 18, 2026 by Kilian Jahn
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	PDF File Updated - adm6.pdf	Jun 18, 2026 by Kilian Jahn
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	PDF File Updated - adm6-xxx-xx.x-xxx-x-x-x-footprint.pdf	Jun 18, 2026 by Kilian Jahn
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	PDF File Updated - adx6.pdf	Jun 18, 2026 by Kilian Jahn
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	PDF File Updated - adx6 mated document-mkt.pdf	Jun 18, 2026 by Kilian Jahn
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Technical Specifications

Absolute Maximum Ratings ^*)

Power Rail Name/ Schematic Name	Description	Max	Unit
12V_input_A	Carrier powered via ATX supply.	20	V
12V_input_B	Carrier powered via barrel jack (2.1 mm).	20	V
5VSB	Only used, when the carrier is powered via an ATX supply / 12V_input_A .	6.5	V

Absolute maximum ratings

^*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

Customer SoC design. The allowed main SoC temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
Cooling solution, active and or passive cooling.
Climate or environmental conditions besides ambient temperature range.
Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).

Parameter	Min	Max	Units
12V_input_A	11.4	12.6	V
12V_input_B	11.4	12.6	V
5VSB	4.5	5.5	V

Recommended operating conditions.

Physical Dimensions

Module size: 170 mm x 170 mm / Mini-ITX form factor. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.
PCB thickness: 1.93 mm ± 0.19 mm.

Physical Dimension

Currently Offered Variants

Trenz shop TEBF0818 overview page*
English page	German page

*) Module article name encoding table: Zynq Ultrascale+ based modules (MPSoC, RFSoC)

Trenz Electronic Shop Overview

Revision History

Hardware Revision History

Hardware revision number can be found on the PCB together with module model number separated by the dash.

Board hardware revision number.

Date	Revision	Changes	Documentation Link
2024-05	REV2A	Added additional label on the Top Overlay layer, removed label "TEBF0818-02" from TOP layer Removed polygon cutout from Top solder mask	REV2A
2023-02	REV02	Q1, Q2 and Q3 changed to MP5077GG (previous Load Switch is EOL), and their external components added. U2 changed to SDINBDG4-8G-XI2 (previous e.MMC is EOL). R14 changed to 2KΩ. J1, J2, J3 and J4 Connectors changed to ADF6-60-03.5-L-4-2-FR. D8 and D10 updated (previous LEDs are EOL). FAN M1 changed to HY45T-05A (previous FAN is EOL). U54 (new) FAN Controller LM96163CISD/NOPB and its external components added. Hardware (screws and nuts) for new FMC FAN updated. J19 Connector changed to 4 Position type 2,54mm pitch. Module orientation mark placed in Silkscreen Top Side. R164 pull-up resistor on PGood of U19 added. R41 changed to 200K and made it fitted in Default and A variants. C93/C94 Capacitors changed to 0R Resistors (now R263/R264). U56 (new) Differential 1:2 LVDS to HCSL Buffer NB3L202KMN and its peripheral components added. One U56 Buffered PCIe REFCLK Output connected to PS-GT BANK input MGTCLKREF in modules. C179, C182, C185, C221, C222 and C223 multi-purpose MGT CLKs capacitors changed to 10nF. C69 and C70 changed to 220nF. T12 added as a Temperature Sensor and connected to U54. L25 added. U55 added. C207, C39 and C82 changed to 10μF and 10V Voltage Rating. U8 (FMC_VADJ) changed to MPM3650CGQW-Z (previous Regulator is EOL). U19 (1.8V) changed to MPM3650CGQW-Z (previous Regulator is EOL). U28 (1.2V) changed to MP2164GG (previous Regulator is EOL). U43 (3V3SB) changed to MP2164GG (previous Regulator is EOL). VID circuit for U8 (FMC_VADJ) implemented for 1.2V, 1.5V and 1.8V selection only. Differential Pair Impedance Directive D90 set in PCIe RX and TX signal paths. C121, C122, C123 and C124 FMC MGT CLKs capacitors changed to 10nF. C197, C200, C202 and C203 SATA Capacitors changed to 10nF. C72 and C73 changed to capacitors with a minimum of 10V Voltage Rating. C263 capacitor added. R175 set as not fitted in all variants. R65 changed to 1KΩ. Power overview added. I2C net (SC_SDA, SC_SCL) for FMC FAN Controller connected to U27 and its slave address label added. L8, L9, L11 and L12 changed to 4.7uH. C47, C48, C50, C52, C57, C58, C60 and C62 changed to 100nF. C49, C51, C59 and C61 changed to 22uF. J14 SFP+ connector and its pull-ups resistors, now sourced from 3.3V_PER. Differential Pair Impedance Directive D100 set where applicable. CAN Bus Differential Pair Impedance Directive set to 120Ohms (H and L net names modified to match). R107 and R108 set as fitted in all variants. C16 and C17 set as not fitted in all variants. J6 pin connections updated 1-to-1 as follows: RX1P/N #NAME? B128_RX0_P/N, RX2P/N #NAME? B128_RX1_P/N RX3P/N #NAME? B128_RX2_P/N, RX4P/N #NAME? B128_RX3_P/N, TX1P/N #NAME? B128_TX0_P/N, TX2P/N #NAME? B128_TX1_P/N TX3P/N #NAME? B128_TX2_P/N, TX4P/N #NAME? B128_TX3_P/N. J21 pin connections updated 1-to-1 as follows: FF_L1_TX to FF_L1_RX, FF_L2_TX to FF_L2_RX, FF_L3_TX to FF_L3_RX, FF_L4_TX to FF_L4_RX. Pull-ups on T7 changed to 5VSB. Series gate resistor and gate pull-down resistor added to T7 and T8. Shield of all J7 connectors (USB and ETH) tied together to FGND net. Shield of J13 connected to FGND2 net. Cage of J14 connected to FGND3 net. PCB Rules updated. Signals layout updated. Layer stack improved. Polygons updated. UKCA marking added.	REV02
2021-05	REV01	Initial release	REV1

Hardware Revision History

Document Change History

Date

Revision

Contributor

Description

2026-04-14

v.31

Kilian Jahn

Drawio Block Diagram JTAG - Link fixed
Drawio .tmp-files removed
Drawio Physical Dimensions & Revision Number - Configuration completed

v.27

Kilian Jahn

Initial document

--

all

Christoph Gellert , ED , Kilian Jahn , Vadim Yunitski

--

Document change history.

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Product Disclaimer

Products (incl. Software and Firmware) are exclusively designed, manufactured, and distributed for industrial applications. They are not intended, authorized, or certified for use in critical safety applications, medical devices, aerospace, nuclear, life-support, traffic-control, military, or other environments where malfunction or failure could result in personal injury, death, or significant property or environmental damage.

Trenz Electronic GmbH (“Manufacturer”) excludes any liability for inappropriate use in such contexts. The Customer bears all responsibility for verifying suitability and compliance with applicable regulations when deploying in any critical-use scenario. The Customer also agrees to indemnify and hold harmless the Manufacturer from any third-party claims or liabilities arising from such use.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.

2025-08-01

Trenz Electronic Documentation

TEBF0818 TRM

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

On-board Peripherals

System Controller

e.MMC

ETH PHY

USB 3.0 PHY

USB 2.0 PHY

HD Audio

FMC connector

SDIO switch

Fan controller

I2C switch

I2C switch

EEPROM

EEPROM with MAC

Pmod

IO Expander

XMOD / TE0790

Bus transceiver

Clock Generator

Clock Fanout

Oscillator programmable 1)

Oscillator CRY

Oscillator