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The Trenz Electronic TEI1000 is a SoM integrating an Altera Stratix 10 SoC or FPGA, DDR4 SDRAM, SPI Flash memory for configuration and operation, an analogue switch for dynamic boot configuration changes and powerful switch-mode power supplies for most on-board voltages. A large number of configurable IOs is provided via high-speed stacking connections in a compact 6 cm x 8 cm form factor.
Refer to https://trenz.org/tei1000-info for current online available documentation.
SoC or FPGA
Altera Device 1) : SX (SoC) / GX (FPGA)
Logic Density 1) : 040
Temperature Range 1) : Commercial / Extended / Industrial 1)
RAM/Storage
On Board
Interface 3)
1.2 V to 1.8 V LVDS: 48x SE / 24x DIFF
Power
Supply Voltage 5.0 V to 12.0 V
Altera Stratix 10, U14
DDR4 SDRAM, U1, U2
B2B connector ADM6, JM1, JM2, JM3
Storage device name | Designator | Content | Notes |
|---|---|---|---|
| SoC | U14 | Not programmed | |
QSPI Flash | U16 | Not programmed | |
DDR4 SDRAM | U1 / U2 | Not programmed | |
System Controller | U4 | Firmware |
Connector Type | Designator | Interface | IO count | Notes |
|---|---|---|---|---|
B2B | JM1 | LVDS | 48x SE / 24x DIFF | 1.8 V Bank 3B |
B2B | JM1 | IO HV | 48x SE | 3.3 V Bank 3C. Can be lowered to 1.8 V via resistors R175 and R234. |
B2B | JM1 | GPIO | 18x SE / 9x DIFF | 1.8 V Bank 3D |
| B2B | JM1 | LVDS | 6x SE / 3x DIFF | 1.8 V Bank 3D |
B2B | JM1 | IO HPS | 48x SE | 1.8 V Bank HPS only for SX devices |
B2B | JM2 | MGT | 18x GXB | Banks 1C/1D/1E/1F |
B2B | JM2 | MGT CLK | 8x GXB CLK | Banks 1C/1D/1E/1F |
B2B | JM2 | LVDS | 48x SE / 24x DIFF | 1.8 V Bank 2L |
B2B | JM3 | LVDS | 48x SE / 24x DIFF | 1.14 V ... 1.89 V Bank 2K |
B2B | JM3 | LVDS | 8x SE / 4x DIFF | 1.8 V Bank B3A |
B2B | JM3 | LVDS | 40x SE / 20x DIFF | 1.8 V Bank B3A |
B2B | JM3 | GPIO | 6x SE | 1.8 V Bank 6A |
B2B | JM3 | IO | 4x SE | 3.3 V System Controller Bank 2 |
Test Point | Top | Bottom | Signal | Notes |
|---|---|---|---|---|
TP1 | x | 1V03 | ||
TP2 | x | DDR_2V5 | ||
TP3 | x | 3V3D_PERM | ||
TP4 | x | DDR_1V2 | ||
TP5 | x | VTT | ||
TP6 | x | PG_S10_VCC | ||
TP7 | x | - | U12 CLKOUT. No net name. | |
TP8 | x | 1V8D | ||
TP9 | x | - | U12 ISHARE. No net name. | |
TP10 | x | 0V9 | ||
TP11 | x | S10_VCCIO3C | ||
TP12 | x | S10_SDM_CLK1 | ||
TP13 | x | S10_VCCFUSEWR_SDM | ||
TP14 | x | S10_VCCIO_B2K | ||
TP15 | x | VCC_CORE | ||
TP16 | x | VCC_SDA | ||
TP17 | x | VCC_CLK | ||
TP18 | x | VCC_CORE | ||
TP19 | x | 1V8_FLT1 | ||
TP20 | x | 1V8_FLT2 | ||
TP21 | x | VCCPLLDIG_SDM | ||
TP22 | x | 1V03 | ||
TP23 | x | DDR_2V5 | ||
TP24 | x | 3V3D_PERM | ||
TP25 | x | DDR_1V2 | ||
TP26 | x | VTT | ||
TP27 | x | VREFA | ||
TP28 | x | VREFA | ||
TP29 | x | 1V8D | ||
TP30 | x | VIN | ||
TP31 | x | 0V9 | ||
TP32 | x | S10_VCCFUSEWR_SDM | ||
TP33 | x | S10_VCCIO3C |
Chip/Interface | Designator | Connected To | Notes |
|---|---|---|---|
Stratix 10 SoC / FPGA | U14 |
| |
DDR4 SDRAM | U1 / U2 |
| |
QSPI Flash | U16 |
| |
Analogue Switch | U21 |
| |
System Controller | U4 |
| |
Oscillator | U5 |
| 25 MHz |
| Oscillator | U15 |
| 100 MHz |
| Oscillator | U17 |
| 100 MHz |
| Oscillator | Y1 |
| 125 MHz for SoC SX and 100 MHz for SoC GX variants. |
Signal Name | Connector.Pin | Direction1) | Description |
|---|---|---|---|
B2B_CLK 2), B2B_SDA 2) | JM3.B30 / JM3.B31 | Signal dependent | I2C. |
S10_NCONFIG 2) | JM3.B32 | IN | Restart configuration. Pulled-up to 1V8D. |
S10_NSTATUS 2) | JM3.B33 | OUT | Synchronise configuration. Pulled-up to 1V8D. |
PWR_ON 2) | JM3.A34 | IN | Enable SoM. Pulled-down to GND. |
PG_3V3D_PERM | JM3.A35 | OUT | Power-good indicator for 3.3 V regulator. Pulled-up to 3V3D_PERM. |
PG_S10_VCCIO 2) | JM3.A36 | - 2) | Firmware dependent usage. |
S10_VCCIO_PG 2) | JM3.A37 | IN | Enable power supply for SoM. |
MAX10_PG 2) | JM3.A38 | OUT | SoM powered-up. |
S10_VCCIO_REQ 2) | JM3.A39 | OUT | Request for bank 2K voltage power supply. Pulled-down to GND. |
PCIE_PERSTN | JM3.C26 | INOUT | PCIe PERST# signal or GPIO. |
PCIE_WAKEN | JM3.C27 | INOUT | PCIe WAKE# signal or GPIO. |
S10_TD0_P / S10_TD0_N / S10_TD1_P/S10_TD1_N | JM3.D28 / JM3.D29 / JM3.D26 / JM3B.D27 | - | Internal temperature sensing diodes. |
S10_TDI / S10_TDO / S10_TCK / S10_TMS | JM3.C32 / JM3.C33 / JM3.C34 / JM3.C35 | Signal dependent | Stratix 10 SDM JTAG. |
S10_UART_RX / S10_UART_TX | JM3.C49 / JM3.C50 | Signal dependent | Stratix 10 UART or GPIO. |
MAX10_CRC_ERROR 2) | JM3B.C55 | OUT | Firmware dependent usage. |
MAX10_TDI_CON / MAX10_TDO_CON / | JM3.C56 / JM3.C57 / JM3.C58 / JM3.C59 | Signal dependent | System Controller JTAG. |
MAX10_JTAGEN_CON 2) | JM3.C60 | IN | System Controller JTAG Selection. Pulled-up to 3V3D_PERM. |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
2) Firmware dependent. Refer to TEI1000 MAX10 Firmware / TEI1000 MAX10 for further information.
Power Rail Name / Schematic Name | Connector.Pin | Direction1) | Notes |
|---|---|---|---|
VIN | JM3.D38 / JM3.D39 / JM3.D40 / JM3.D41 / JM3.D42 / JM3.D43 / JM3.D44 / JM3.D45 | IN | Main SoM power supply. |
S10_VCCIO_B2K | JM3.A25 | IN | SoC/FPGA Bank 2K power supply. |
1V8D | JM3.A26 / JM3.C29 / JM3.C30 | OUT | SoM module power supply. |
S10_VCCIO3C | JM1.A33 | OUT | SoM module power supply. |
VREF_B3A | JM3.A29 | IN | Input reference bank 3A voltage. |
VREF_B3B | JM1.A32 | IN | Input reference bank 2L and 3B voltage. |
VREF_B3C | JM1.B32 | IN | Input reference bank 3C voltage. |
VREF_B3D | JM1A.B33 | IN | Input reference bank 3D voltage. |
VREF_B2K | JM3A.A28 | IN | Input reference bank 2K voltage. |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
| Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
|---|---|---|---|---|---|
| 0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. |
| 1 | VIN | 5.0 V to 12 V | - | SoM power supply. | |
| 2 | PWR_ON 2) | 3.3 V | Pull Down 3) | SoM enable. | |
| 3 | S10_VCCIO_REQ 2) | 3.3 V | Pull Down3) | SoM asks baseboard to enable bank 2K voltage power supply. | |
| 4 | S10_VCCIO_PG 2) | 3.3 V | - | Proceed SoM power sequence after bank 2k bank supply enable. | |
| 5 | MAX10_PG 2) | 3.3 V | Pull Down 3) | SoM power up sequence done. |
1) This note was removed.
2) Firmware dependent. Refer to TEI1000 MAX10 Firmware / TEI1000 MAX10 for further information.
3) Already implemented by this SoM.
The carriers use Samtec AcceleRate HD High-Density on top side.
When using the same type on baseboard, the mating height is 5 mm. Other mating heights are possible by using connectors with a different height:
| Order number | REF number | Samtec Number | Type | Contribution to stacking height | Comment |
|---|---|---|---|---|---|
| 30095 | REF-30095 | ADM6-60-01.5-L-4-2 | Module connector | 1.5 mm | Standard connector used on modules (legacy) |
| - | - | ADM6-60-01.5-L-4-0 | Module connector | 1.5 mm | Alternative connector |
| 31137 | REF-31137 | ADF6-60-03.5-L-4-2 | Baseboard connector | 3.5 mm | Standard connector used on carrier (legacy) |
| - | - | ADF6-60-03.5-L-4-0 | Baseboard connector | 3.5 mm | Alternative connector |
The module can be manufactured using other connectors upon request.
The AcceleRate HD High-Density connector speed rating depends on the stacking height; please see the following table:
| Connector | Stacking height | Speed rating |
|---|---|---|
| ADM6-XX-XX.X-X-X-2 | 5 mm | 56 Gbps |
| ADM6-XX-XX.X-X-X-0 | 5 mm | 64 Gbps |
Current rating of Samtec AcceleRate HD High-Density B2B connectors is 1.34 A per pin (4 pins powered).
| File | Modified | |
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| PDF File 20200225_hsc_adm6-xx-01p5-xxx-4-a_adf6-xx-03p5-xxx-4-a.pdf | Mar 04, 2022 by ED | |
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| PDF File adf6.pdf | Mar 04, 2022 by ED | |
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| PDF File adm6.pdf | Mar 04, 2022 by ED | |
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| PDF File adm6-xxx-xx.x-xxx-4-x-x-xr-mkt.pdf | Mar 04, 2022 by ED | |
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| PDF File adm6-xxx-xx.x-xxx-x-x-x-footprint.pdf | Mar 04, 2022 by ED | |
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| PDF File Updated - 20200225_hsc_adm6-xx-01p5-xxx-4-a_adf6-xx-03p5-xxx-4-a.pdf | Jun 18, 2026 by Kilian Jahn | |
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| PDF File Updated - adm6.pdf | Jun 18, 2026 by Kilian Jahn | |
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| PDF File Updated - adm6-xxx-xx.x-xxx-x-x-x-footprint.pdf | Jun 18, 2026 by Kilian Jahn | |
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| PDF File Updated - adx6.pdf | Jun 18, 2026 by Kilian Jahn | |
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| PDF File Updated - adx6 mated document-mkt.pdf | Jun 18, 2026 by Kilian Jahn | |
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Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
|---|---|---|---|---|
VIN | Supply power from carrier. | -0.3 | 14 | V |
S10_VCCIO_B2K | Stratix 10 bank 2k power supply. | -0.5 | 2.19 | V |
*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.
The categories are:
These categories do not take into account the entire custom system consisting of:
Classification of the module can be looked up here: Article Number Information i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.
The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.
The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).
Parameter | Min | Max | Unit | Reference Document |
|---|---|---|---|---|
VIN | 5.0 | 12.0 | V | |
S10_VCCIO_B2K | 1.14 | 1.89 | V | Altera Stratix 10 Device Datasheet |
Module size: 60 mm × 80 mm - Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.
All dimensions are shown in millimeters.
Trenz shop TEI1000 overview page* | |
|---|---|
*) Module article name encoding table: Altera Stratix 10 GX and SX based modules
The hardware revision number is located on the PCB next to the module identifier, separated by a dash.
Date | Revision | Changes | Documentation Link |
|---|---|---|---|
| 2024-06 | 02 | 1. Changed pulldowns to 1K for all power sequencing groups. Corrected notes about enable thresholds of voltage regulators and load switches. 40. Added test points to the voltage rails on the TOP side | |
| - | 01 | Initial release |
Date | Revision | Contributor | Description |
|---|---|---|---|
| |||
2026-07-31 | v.7 | Kilian Jahn |
|
2025-07-11 | v.6 | Kilian Jahn |
|
2025-06-30 | v.3 | Kilian Jahn |
|
2025-06-27 | v.2 | Kilian Jahn |
|
-- | all |
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