Affected Product | Effected Changes | Status* | CPLD | Change Log current development state | Link to current firmware description |
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TEM0007 | #? | Unprocessed | LCMXO2-256HC |
| currently not available |
TE0710 | #? | Unprocessed | LCMXO2-256HC |
| TE0710 CPLD |
TE0711 | #? | Unprocessed | LCMXO2-256HC |
| TE0711 CPLD |
TE0712 | #3,#4,#5,#6 | Test phase | LCMXO2-256HC | Renaming the port signals according to the schematic. Defining and reading CPLD Revision via I2C interface. JTAG signal timing adjustment Adding I2C to gpio ip (i2c_slave.vhd) LED function was changed.
| TE0712 CPLD |
TE0713 | #? | Unprocessed | LCMXO2-256HC |
| TE0713 CPLD |
TE0715 | #1,#2,#3,#4,#5,#6 | Test phase | LCMXO2-256HC | Adding boot mode configuration via hardware (dip switch) and firmware (CPLD) PGOOD pin is used as boot mode selector pin. Pullup or pulldown states of PORT pins was checked. Adding I2C to gpio ip (i2c_slave.vhd) Changing oscillator frequency from 12.09 MHZ to 24.18MHZ PORT signals according to the schematic are renamed. JTAG time constraint correcture Adding boot mode the option configuration via linux console
| TE0715 CPLD |
TE0720 | #1,#2,#5,#6,#7 (#4 since CPLD Rev06) | Test phase | LCMXO2-1200HC | Added matched functions for WDT Chip BD39040MUF-CE2 PG_ALL pin pulled up. User can activate WDT as before. If no WDT chip on the board, hardware WDT will be switched automatically on software WDT. Using CR5[15:14] to save the WDT status ("00" --> WDT deactive, "01" Hardware WDT, "10" Software WDT) Using Register4 of mdio_slave_interface to see WDT status via the following instruction in linux: phytool read eth0/0x1A/4 Boot mode configuration via mdio interface (phytool) PGOOD pin is used as boot mode selector pin. - NOSEQ
NOSEQ pin is used as tristate via i2c interface. Reseting the FPGA after boot mode configuration Matched to FSBL code to show all informations while booting in linux console. For example Boot mode, pudc state ... Monitoring CR4[15:8] and CR5[10] continuously, to implement a state machine for boot mode configuration correctly. Using CR4[15:12] as control bit to reset FPGA Using CR4[9:8] as boot mode configuration , if the FPGA is not restarted still via soft reset. Defining a neu input register for mdio_slave_interface (CR5) Using CR5[9:8] as boot mode configuration, if the FPGA is restarted already via soft reset. Using CR5[10] to monitor , if the FPGA is restarted already via soft reset. Using Register4 to read the generic parameters and other parameters via FSBl code or phytool command in linux : Phytool read eth0/0x1A/4 Using i2c_slave.vhd instead of I2C_to_GPIO.v Changing Firmware Register MDIO_SL_REGISTER_4_CONTENT to CPLD_REVISION register.
| TE0720 CPLD |
TE0741 | #1,#4,(#5 still in process) | Processing | LCMXO2-256HC | | TE0741 CPLD |
TE0820 | #1,#2,#3,#4,#5,#6 | Processing | LCMXO2-256HC | Adding configuration of boot mode in linux console and via generic parameters PGOOD pin used as boot mode selector pin. Adding boot mode configuration via hardware JTAG time constraint correcture Adding I2C to gpio ip (i2c_slave.vhd) LED function was changed.
| TE0820 CPLD |
TE0821 | #1,#2,#3,#4,#5,#6 | Processing | LCMXO2-256HC | Adding configuration of boot mode in linux console and via generic parameters PGOOD pin used as boot mode selector pin. Adding boot mode configuration via hardware JTAG time constraint correcture Adding I2C to gpio ip (i2c_slave.vhd) LED function was changed.
| TE0821 CPLD |
TE0823 | #1,#2,#3,#4,#5,#6 | Processing | LCMXO2-256HC | Adding configuration of boot mode in linux console and via generic parameters PGOOD pin used as boot mode selector pin. Adding boot mode configuration via hardware JTAG time constraint correcture Adding I2C to gpio ip (i2c_slave.vhd) LED function was changed.
| TE0823 CPLD |
TE0841 | #? | Unprocessed | LCMXO2-256HC |
| TE0841 CPLD |
TE0701 | #2, #4 | Test phase | LCMXO2-1200HC | - Connecting PGOOD to CM2 to use as boot mode pin selector
- JTAG timing correction
| TE0701 CPLD |
TE0703 | #? | Unprocessed | LCMXO2-1200HC |
| TE0703 CPLD - CC703S |
TE0705 | #2, #3, #4 | Test phase | LCMXO2-1200HC | Access to CPLD chip of TE0715 USR0 is used as PGOOD, if Access_to_TE0715_CPLD is activated. USR1 is used as JTAGMODE signal of TE0715 CPLD chip. USR1 = ON --> Access to FPGA , USR1 = OFF --> Access to CPLD USR2 is used as selector signal to access to TE0715 CPLD , if Access_to_TE0715_CPLD variable is 2. JTAG Timing correction
| TE0705 CPLD |
TE0706 | #? | HW changes | --- | --- | --- |
TEBA0841 | #? | HW changes | --- | --- | --- |
TEF1002 | #? | Unprocessed | 10M08 |
| TEF1002 SC CPLD MAX10 |
TEB0707 | #? | Unprocessed | 10M08 |
| TEB0707 MAX10 CPLD |