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  • JTAG routing
  • UART routing
  • LED control
  • Power control
  • Reset
  • Configuration mode selection
  • programming Oscillator SI5345A

Firmware Revision and supported PCB Revision

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Product Specification

Port Description

Name / opt. VHD NameDirectionPinBank PowerDescription

BASE_BTN1

inC93.3VUser button "USER_BTN1" from carrier board TEIB0006 (B2B connector → J2-152)
BASE_BTN2inB33.3VUser button "USER_BTN2" from carrier board TEIB0006 (B2B connector → J2-154)
BASE_LED1outA63.3VLed "LED1" from carrier board TEIB0006 (B2B connector → J2-146)
BASE_LED2outA33.3VLed "LED2" from carrier board TEIB0006 (B2B connector → J2-148)
DATA0inN51.8VIOData input signal from Intel Cyclone 10 GX
→ Pin AE10
DEVCLRn
DEVCLRNoutJ51.8VIODevice-wide reset, Intel Cyclone 10 GX
→ Pin AC12
DIS_
1
GROUP1outK123.3VFast Discharging
- connected to GND
DIS_
2
GROUP2outK103.3VFast Discharging
- connected to GND
DIS_
3
GROUP3outJ93.3VFast Discharging
- connected to GND
DIS_
4
GROUP4outJ123.3VFast Discharging
- connected to GND
EN_0V9outE93.3VPower enable signal 0.9V
EN_0V95outJ103.3VPower enable signal  0.95V
EN_1V8outD93.3VPower enable signal 1.8V
EN_1V8MBoutH93.3VPower enable signal 1.8V for carrier board TEIB0006 (B2B connector → J2-86)
EN_1V8VIOoutL123.3VPower enable signal 1.
8V IO
8VIO
EN_1V35outD123.3VPower enable signal 1.35V
EN_3V3MBoutA113.3VPower enable signal 3.3V for carrier board TEIB0006 (B2B connector → J2-74)
EN_VTToutC113.3VPower enable signal VTT
LED1out
F_TCK_OUToutN21.8VIOJTAG, Intel Cyclone 10 GX
F_TDI_OUToutM21.8VIOJTAG, Intel Cyclone 10 GX
F_TDO_INinM31.8VIOJTAG, Intel Cyclone 10 GX
F_TMS_OUToutK11.8VIOJTAG, Intel Cyclone 10 GX
I2C_SCLbidirK21.8VIOClock signal for I2C interface
I2C_SDAbidirL21.8VIOData signal for I2C interface
LED_FP_1outB13
B12
3.3V
status
red led D1,
red led D1
status led for Intel Cyclone 10 GX
LED_FP_2
LED2
outB113.3Vgreen led D2
/currently unused - connected to GNDLED3
, status led for power sequencer core
LED_FP_3outA123.3Vuser defined, green led D3
LED4
LED_FP_4outB123.3Vuser defined, green led D4
MSEL0outM71.8VIOconfiguration mode selection, Intel Cyclone 10 GX
MSEL1outM91.8VIOconfiguration mode selection, Intel Cyclone 10 GX
NCONFIGoutM81.8VIOFPGA configuration pin, Intel Cyclone 10 GX
NSTATUSinM51.8VIOFPGA configuration pin, Intel Cyclone 10 GX
PG_0V9inE103.3VPower Good signal 0.9V, U4
PG_0V95inH103.3VPower Good signal 0.95V, U7
PG_1V8inF83.3VPower Good signal 1.8V, U5
PLL
PG_
RST
1V8VIOin
out
K11
L3
3.3VPower Good signal 1.8VIO
Clock reset
,
SI5345A
U6
RXD
PG_
IN
1V35inE12
N6
3.3VPower Good signal 1.
8VIOUART, Intel Cyclone 10 GX
35V, U8
PG_VTTinD113.3VPower Good signal VTT_DDR, U9
PHY1_33LED1outF10
TXD_OUToutK51.8VIOUART, Intel Cyclone 10 GXRXD_OUToutA10
3.3V
UART, B2B connector
green led from RJ45-connector on carrier board TEIB0006 (B2B connector → J2-67)
PHY1_33LED2outF9
TXD_INinB10
3.3V
UART, B2B connector
yellow led from RJ45-connector on carrier board TEIB0006 (B2B connector → J2-69)
PHY1_LED1inJ11.8VIOled output pin from ethernet phy U2 for PHY1_33LED1
PHY1_LED2inH51.8VIOled output pin from ethernet phy U2 for PHY1_33LED2
PLL_RSToutL31.8VIODevice reset for porgrammable oscillator SI5345A, U14
TCK_INinG23.3VJTAG, B2B
connector →
connector → J2-157
TDI_INinF53.3VJTAG, B2B
connector →
connector → J2-159
TDO_OUToutF63.3VJTAG, B2B
connector →
connector → J2-158
TMS_INinG13.3VJTAG, B2B
connector →
connector → J2-160
TCK
UART_RXD_
OUT
IN
out
in
N2
N61.8VIO
JTAG
UART, Intel Cyclone 10 GX
TDI
UART_RXD_OUTout
M2
A10
1
3.
8VIO
3V
JTAG, Intel Cyclone 10 GX
UART, B2B connector → J2-151
UART_TXD
TDO
_INin
M3
B10
1
3.
8VIO
3V
JTAG, Intel Cyclone 10 GX
UART, B2B connector → J2-153
UART_TXD
TMS
_OUTout
K1
K51.8VIO
JTAG
UART, Intel Cyclone 10 GX
nCONFIG
VADJ_ENoutC123.3VOutput enable signal for voltage regulator U11
VADJ_VS0outF123.3VVoltage selection signal for voltage regulator U11
VADJ_VS1outE133.3VVoltage selection signal for voltage regulator U11
VADJ_VS2out
M8
F13
1
3.
8VIOFPGA configuration pin, Intel Cyclone 10 GX
3VVoltage selection signal for voltage regulator U11
M10_CLK
nSTATUS
in
M5
G9
1
3.
8VIO
3VClock input signal, 25 MHz
FPGA configuration pin, Intel Cyclone 10 GX


Functional Description

JTAG

JTAG access to TEI0006 SoM only through B2B connector J2 available. The JTAG signals are routed directly from B2B connector through Intel MAX 10 to Intel Cyclone 10 GX.

Access between Intel MAX 10 and Intel Cyclone 10 GX can be multiplexed selected via JTAGEN. JTAGEN pin is already pulled up to 3.3V for access to Intel MAX 10, for . For access to Intel Cyclone 10 GX JTAGEN pin has to pulled down to GND on B2B connector J2-105.

...

BASE_LED1 (B2B connector → J2-146) and the nCONFIG NCONFIG Pin from Intel Cyclone 10 GX are connected to user button BASE_BTN1 (B2B connector → J2-152).

BASE_LED2 (B2B connector → J2-148) is connected to user button BASE_BTN2 (B2B connector → J2-154).

LED1 LED_FP_1 is connected to nSTATUS NSTATUS pin from Intel Cyclone 10 GX.

LED2 LED_FP_2 is connected to GND.the fault status signal of the power sequencer core.

ON → no fault detected

OFF → fault detected

LED_FP_3 and LED_FP_4 LED3 and LED4 are connected to DATA0 pin from Intel Cyclone 10 GX.

Power control

EN_0V9 is set constant to logical one and enables power regulator U4 for 0.9V.

If power good signal PG_0V9 from power regulator U4 is set to logical one, output pin EN_0V95 is set to logical one and enables power regulator U7 for 0.95V.

If power good signal PG_0V95 from power regulator U4 is set to logical one, output pin EN_1V8 is set to logical one and enables power regulator U5 for 1.8V.

If power good signal PG_1V8 from power regulator U4 is set to logical one,

  • output pin EN_1V8VIO is set to logical one and enables power regulator U6 for 1.8VIO,
  • output pin EN_3V3MB is set to logical one  (connnected to J2-74 → enables power regulator U3 on carrier board TEIB0006),
  • output pin EN_1V8MB is set to logical one (connected to J2-86 → enables power regulator U12 on carrier board TEIB0006),
  • output pin EN_1V35 is set to logical one and enables power regulator U8 for 1.35V (VDD_DDR),
  • output pin EN_VTT is set to logical one and enables power regulator U9 for VTT_DDR.

Reset

PHY1_LED1 is directly connected with PHY1_33LED1.

PHY1_LED2 is directly connected with PHY1_33LED2.

Power control

All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals.

Output voltage VADJ of power regulator U11 is set to 1.8V via VADJ_VS0 pin, VADJ_VS1 pin and VADJ_VS2 pin (Pins are set to logical one).

Reset

DEVCLRN (Device-wide reset) pin for Intel Cyclone 10 GX DEVCLRn (Device-wide reset) and clock reset PLL_RST for the programmable Oscillator SI5345A are set constant to logical one.

Configuration mode selection

MSEL0 and MSEL1 are set constant to logical one. The selected configuration mode is "AS / Standard".

Programmable Oscillator SI5345A

The volatile memory of the programmable Oscillator SI5345A is configured via I2C interface with following clock frequencies.

PLL outFrequencyI/O Standard
OUT0100 MHzLVDS
OUT1100 MHzLVDS
OUT2100 MHzLVCMOS
OUT3unused--
OUT4unused--
OUT5200 MHzLVDS
OUT6100 MHzLVDS
OUT7125 MHzLVDS
OUT8100 MHzLVDS
OUT9125 MHzLVDS

Appx. A: Change History and Legal Notices

Revision Changes

  • REV02 to REV03
    • add Power Sequencer Core
    • programm Oscillator SI5345A via I2C interface
  • REV01 to REV02
    • add VADJ configuration for power regulator U11

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
prefixv.

REV1REV3REV1REV2

Page info
modified-user
modified-user

  • add power sequencer
  • programming Oscillator SI5345A
2019-08-27v.1REV1REV1Thomas Dück
  • Initial release

All

Page info
modified-users
modified-users


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