Page History

Renaming the port signals according to the schematic.

Defining and reading CPLD Revision via I2C interface.

JTAG signal timing adjustment

Adding I2C to gpio ip (i2c_slave.vhd)

LED function was changed.

Adding boot mode configuration via hardware (dip switch) and firmware (CPLD)

PGOOD pin is used as boot mode selector pin.

Pullup or pulldown states of PORT pins was checked.

Adding I2C to gpio ip (i2c_slave.vhd)

Changing oscillator frequency from 12.09 MHZ to 24.18MHZ

PORT signals according to the schematic are renamed.

JTAG time constraint correcture

Adding boot mode the option configuration via linux console 

Added matched functions for WDT Chip BD39040MUF-CE2

 PG_ALL pin pulled up.

User can activate WDT as before.

If no WDT chip on the board, hardware WDT will be switched automatically on software WDT.

Using CR5[15:14] to save the WDT status ("00" --> WDT deactive, "01" Hardware WDT, "10" Software WDT)

Boot mode configuration via mdio interface (phytool)

PGOOD pin is used as boot mode selector pin. 

 NOSEQ pin is used as tristate via i2c interface.

Reseting the FPGA after boot mode configuration

Matched to FSBL code to show all informations while booting in linux console. For example Boot mode, pudc state ...

Monitoring CR4[15:8] and CR5[10] continuously, to implement a state machine for boot mode configuration correctly.

Using CR4[15:12] as control bit to reset FPGA

Using CR4[9:8] as boot mode configuration , if the FPGA is not restarted still via soft reset.

Defining a neu input register for mdio_slave_interface (CR5)

Using CR5[9:8] as boot mode configuration, if the FPGA is restarted already via soft reset.

Using CR5[10] to monitor , if the FPGA is restarted already via soft reset.

Using Register4 to read the generic parameters and other parameters via FSBl code or phytool command in linux : Phytool read eth0/0x1A/4

Using i2c_slave.vhd instead of I2C_to_GPIO.v

Changing Firmware Register MDIO_SL_REGISTER_4_CONTENT to CPLD_REVISION register. 

Added one wire slave and master in code. But it works only , when the clock of master and slave are synchronized. Therefore one wire master and slave is added only in simulation and not in synthesis.

Adding configuration of boot mode in linux console and via generic parameters

PGOOD pin used as boot mode selector pin.

Adding boot mode configuration via hardware

JTAG time constraint correcture

Adding I2C to gpio ip (i2c_slave.vhd)

LED function was changed.

Adding configuration of boot mode in linux console and via generic parameters

PGOOD pin used as boot mode selector pin.

Adding boot mode configuration via hardware

JTAG time constraint correcture

Adding I2C to gpio ip (i2c_slave.vhd)

LED function was changed.

Adding configuration of boot mode in linux console and via generic parameters

PGOOD pin used as boot mode selector pin.

Adding boot mode configuration via hardware

JTAG time constraint correcture

Adding I2C to gpio ip (i2c_slave.vhd)

LED function was changed.

Access to CPLD chip of TE0715

USR0 is used as PGOOD, if Access_to_TE0715_CPLD is activated.

USR1 is used as JTAGMODE signal of TE0715 CPLD chip. USR1 = ON --> Access to FPGA , USR1 = OFF --> Access to CPLD

USR2 is used as selector signal to access to TE0715 CPLD , if Access_to_TE0715_CPLD variable is 2.

JTAG Timing correction