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Table of Contents
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Overview
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Refer to https://wiki.trenz-electronic.de/display/PD/TE0745+TRM for online version of this manual and the rest of the available documentation. |
The Trenz Electronic TE0745 is an industrial-grade module integrating a Xilinx Zynq SoC (XC7Z-030, XC7Z-035 or XC7Z-045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.
Key Features
Industrial/Commercial/Expanded grade Xilinx Zynq SoC (XCZ7030, XC7Z035, XC7Z045)
- 250 FPGA PL I/Os (120 LVDS pairs possible)
- 17 PS MIOs on B2B connector available
- Temperature Grade: Expanded (-40 to +100 °C)
- Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
- DDR3L SDRAM, 512MB or 1GB , 16 bit width address
- 32 or 64 MByte QSPI Flash memory
- 4 or 8 GTX transceiver lanes (XC7Z030 has 4)
- Gigabit Ethernet transceiver PHY
- EEPROM for storing Ethernet MAC Address
- Hi-speed USB 2.0 ULPI transceiver with full OTG support
- Programmable quad clock generator
- Temperature compensated RTC (real-time clock)
- Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
- On-board high-efficiency DC-DC converters
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- User LED
- Evenly-spread supply pins for good signal integrity
- Rugged for shock and high vibration
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
Figure 1: TE0745-02 Block Diagram.
Main Components
Figure 2: TE0745-02 SoC module.
- Xilinx Zynq XC7Z family SoC, U1
- 256 Mbit Quad SPI Flash memory Micron N25Q256A, U12
- Reference clock signal oscillator SiTime SiT8008BI @33.333333 MHz, U12
- Reference clock signal oscillator SiTime SiT8008BI @25.000000 MHz, U9
- Marvell Alaska 88E1512 Gigabit Ethernet PHY, U7
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16-bit word width), U3
- TI TPS51206 DDR3 memory termination regulator with buffered reference voltage VTTREF, U18
- Intersil ISL12020MIRZ Real-Time-Clock, U24
- TI TCA9517 level-shifting I2C bus repeater, U17
- Red LED, D2
- Green LED, D1
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 banks a 32 MWords, 16 Bit word width), U5
- Altera Enpirion EN63A0QI 12A DC-DC PowerSoC @1.0V (VCCINT), U4
- TI TPS74401RGW LDO DC-DC regulator @1.2V (MGTAVTT), U8
- TI TPS72018DRVR LDO DC-DC regulator @1.8V (MGTAUX), U6
- TI TPS74401RGW LDO DC-DC regulator @1.0V (MGTAVCC), U11
- Silicon Labs Si5338A I2C Programmable Quad Clock Generator, U13
- Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
- 256 Mbit Quad SPI Flash memory (Micron N25Q256A), U14
- Microchip USB3320 USB transceiver PHY , U32
- Reference clock signal oscillator SiTime SiT8008BI @52.000000 MHz, U33
- Microchip 24AA025E48 EEPROM for MAC address, U23
- Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
Initial Delivery State
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Storage Device Name
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Content
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Notes
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24AA025E48 EEPROM
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User content, not programmed
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SPI Flash OTP Area
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Empty, not programmed
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Except serial number programmed by flash vendor.
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SPI Flash Quad Enable bit
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Programmed
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SPI Flash main array
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Not programmed
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eFUSE USER
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Not programmed
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eFUSE Security
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Not programmed
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Table 1: Initial delivery state.
Signals, Interfaces and Pins
Board to Board (B2B) I/O's
The B2B connectors are high-speed hermaphroditic stacking strips providing modular interface to the SoC's PL and PS I/Os. Both single ended and differential signaling LVDS pairs are supported.
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All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.
For detailed information about the pin-out, please refer to the Pin-out Table.
The configuration of the I/O's MIO0, MIO12 ... MIO15 and MIO40 ... MIO51 are depending on the base-board peripherals connected to these pins.
MGT Lanes
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pair, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
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- MGT_RX0_P
- MGT_RX0_N
- MGT_TX0_P
- MGT_TX0_N
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- J3-50
- J3-52
- J3-51
- J3-53
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- MGTHRXP0_112, AB4
- MGTHRXN0_112, AB3
- MGTHTXP0_112, AA2
- MGTHTXN0_112, AA1
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- MGT_RX1_P
- MGT_RX1_N
- MGT_TX1_P
- MGT_TX1_N
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- J3-56
- J3-58
- J3-57
- J3-59
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- MGTHRXP1_112, Y4
- MGTHRXN1_112, Y3
- MGTHTXP1_112, W2
- MGTHTXN1_112, W1
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- MGT_RX2_P
- MGT_RX2_N
- MGT_TX2_P
- MGT_TX2_N
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- J3-62
- J3-64
- J3-63
- J3-65
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- MGTHRXP2_112, V4
- MGTHRXN2_112, V3
- MGTHTXP2_112, U2
- MGTHTXN2_112, U1
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- MGT_RX3_P
- MGT_RX3_N
- MGT_TX3_P
- MGT_TX3_N
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- J3-68
- J3-70
- J3-69
- J3-71
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- MGTHRXP3_112, T4
- MGTHRXN3_112, T3
- MGTHTXP3_112, R2
- MGTHTXN3_112, R1
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- MGT_RX4_P
- MGT_RX4_N
- MGT_TX4_P
- MGT_TX4_N
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- J1-23
- J1-21
- J1-22
- J1-20
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- MGTHRXP0_111, AD8
- MGTHRXN0_111, AD7
- MGTHTXP0_111, AF8
- MGTHTXN0_111, AF7
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- MGT_RX5_P
- MGT_RX5_N
- MGT_TX5_P
- MGT_TX5_N
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- J1-17
- J1-15
- J1-16
- J1-14
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- MGTHRXP1_111, AE6
- MGTHRXN1_111, AE5
- MGTHTXP1_111, AF4
- MGTHTXN1_111, AF3
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- MGT_RX6_P
- MGT_RX6_N
- MGT_TX6_P
- MGT_TX6_N
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- J1-11
- J1-9
- J1-10
- J1-8
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- MGTHRXP2_111, AC6
- MGTHRXN2_111, AC5
- MGTHTXP2_111, AE2
- MGTHTXN2_111, AE1
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- MGT_RX7_P
- MGT_RX7_N
- MGT_TX7_P
- MGT_TX7_N
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- J1-5
- J1-3
- J1-4
- J1-2
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- MGTHRXP3_111, AD4
- MGTHRXN3_111, AD3
- MGTHTXP3_111, AC2
- MGTHTXN3_111, AC1
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Below are listed MGT banks reference clock sources.
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1) Note: MGT bank 111 not available at XC7Z030 Zynq SoC.
JTAG Interface
JTAG interface access is provided through the SoC's PS configuration bank 0 and is available on B2B connector J1.
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Table 5: JTAG interface signals.
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System Controller I/O's
Following special purpose pins are connected to System Controller CPLD:
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During normal operating mode the JTAG_EN pin should be in the low state for JTAG signals to be forwarded to the Zynq SoC.
If JTAG_EN pin is set to high or left open the JTAG signals are forwarded to the System Controller CPLD.
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Overview
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The Trenz Electronic TE0745 is an industrial/commercial/extended grade module integrating a Xilinx Zynq SoC (XC7Z-030, XC7Z-035 or XC7Z-045), 1 GByte DDR3/L SDRAM, 32/64 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.
Refer to http://trenz.org/te0745-info for the current online version of this manual and other available documentation.
Key Features
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Industrial grade Xilinx Zynq SoC (XCZ7030, XC7Z035, XC7Z045)
- 250 FPGA PL I/Os (120 LVDS pairs possible)
- 17 PS MIOs on B2B connector available
- Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
- 32 (2x16)-bit wide 1GB DDR3L SDRAM
- 32/64 MByte QSPI Flash memory
- 4 or 8 GTX transceiver lanes (XC7Z030 variant has 4)
- 1 Gigabit Ethernet transceiver PHY
- Two User LEDs
- EEPROM for storing Ethernet MAC Address
- Hi-speed USB 2.0 ULPI transceiver with full OTG support
- Programmable quad clock generator
- Temperature compensated RTC (real-time clock)
- Board to Board (B2B)
- Plug-on module with 3 × 160-pin high-speed connectors
- Power Supply
- 3.3 V
- Others:
- On-board high-efficiency DC-DC converters
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Evenly-spread supply pins for good signal integrity
- Rugged for shock and high vibration
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
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Main Components
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- Xilinx Zynq XC7Z family SoC, U1
- Quad SPI Flash memory, U14
- Reference clock signal oscillator, U12
- Reference clock signal oscillator, U9
- 1 Gigabit Ethernet PHY, U7
- DDR3L SDRAM (8 Banks a 32 MWords, 16-bit word width), U3
- DDR3 memory termination regulator with buffered reference voltage VTTREF, U18
- Real-Time-Clock, U24
- level-shifting I2C bus repeater, U17
- Red LED, D2
- Green LED, D1
- DDR3L SDRAM (8 Banks a 32 MWords, 16-bit word width), U5
- 12A DC-DC PowerSoC (VCCINT), U4
- DC-DC regulator (MGTAVTT), U8
- DC-DC regulator (MGTAUX), U6
- DC-DC regulator (MGTAVCC), U11
- I2C Programmable Quad Clock Generator, U13
- Reference clock signal oscillator, U21
- B2B Connector, J3
- B2B Connector, J1
- B2B Connector, J2
- Quad SPI Flash memory, U14
- USB transceiver PHY , U32
- Reference clock signal oscillator, U33
- EEPROM for MAC address, U23
- System Controller CPLD, U2
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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Configuration Signals
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BOOTMODE is connected to MIO4 and B2B Connector J2 (Pin 133) and BOOTMODE_1 is connected to MIO5 and System Controller CPLD and default high.
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Control line which sets in conjunction with signal 'BOOTMODE1' (B2B-pin J2-133)
the boot source of the Zynq chip. See section "Boot Modes".
Permanent logic high in standard SC-CPLD firmware.
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Low active Enable-signal for activating PL supply voltage.
Permanent logic high in standard SC-CPLD firmware.
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Table 6: System Controller CPLD special purpose I/O pins.
Quad SPI Interface
Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
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Table 7: MIO-pin assignment of the Quad SPI Flash memory IC.
Gigabit Ethernet Interface
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.
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PHY_LED0: J2-144
PHY_LED1: J2-146
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Table 8: Ethernet PHY interface connections.
USB Interface
USB PHY (U32) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).
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Table 9: USB PHY interface connections.
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
I2C Interface
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Except the on-module RTC (U24), all other on-module I2C slave devices are operating with the reference voltage PS_1.8V.
I2C addresses for on-module devices are listed in the table below:
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Boot Process
TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21 (permanent logic high in standard SC-CPLD firmware).The boot mode selection will be set by the Zynq's PS MIO pins MIO3...MIO5.
Following table describes how to set the control lines to configure the boot mode:
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JTAG
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Table 13: Selectable boot modes.
In delivery state of the SoM the boot mode depends on the configured SC-CPLD firmware. Basically MIO5 is set to 1 and JTAG is in cascade.
On-board Peripherals
System Controller CPLD
The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
Quad SPI Flash Memory
On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.
High-speed USB ULPI PHY
Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).
MAC Address EEPROM
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I2C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.
Programmable PLL Clock (Phase-Locked Loop)
There is a Silicon Labs I2C programmable quad PLL clock generator Si5338A (U16) on-board. It's output frequencies can be programmed by using the I2C-bus with address 0x70.
A 25 MHz (U21) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.
Once running, the frequency and other parameters can be changed by programming the device using the I2C-bus connected between the Zynq module (master) and reference clock signal generator (slave).
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IN1
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CLKIN_P
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Reference input clock from base board.
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IN3
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Reference input clock.
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IN4
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IN5
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CLK0A
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MGT_CLK1_P
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MGT bank 112 reference clock.
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MGT_CLK3_P
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Table 14: Programmable quad PLL clock generator inputs and outputs.
Oscillators
The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:
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SiTime SiT8008BI oscillator, U12
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Table 15: Clock sources overview.
On-board LEDs
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D1
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Green
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D2
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Red
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Zynq chip (U1), bank 0 (config bank), 'DONE' (pin W9)
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Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.
This LED remains OFF if System Controller CPLD can not power up the PL supply voltage.
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MGT Lanes
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1) Note: MGT bank 111 not available at XC7Z030 Zynq SoC.
MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example:
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory 256/512 Mbit (32/64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used. Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
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DDR3 SDRAM
The TE0745 SoM has two volatile Intelligent Memory 512 MByte DDR3L-1600 SDRAM IC for storing user application code and data.
- Part number: IM4G16D3FABG-125I
- Supply voltage: 1.5V
- Organization: 256M x 16 bits
DDR3 SDRAM can be varied on demand for other assembly options. DDR3 can have density of maximum 512MB due to available addressing. The maximum possible speed for DDR3 SDRAM is 1600 Mb/s.
RTC
An temperature compensated is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I2C bus at slave address mentioned in the table below. General purpose RAM of the RTC can be accessed at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.
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Programmable PLL Clock
There is a Silicon Labs I2C programmable quad PLL clock generator (U16) on-board. It's output frequencies can be programmed by using the I2C-bus with address 0x70.
A 25.00 MHz (U21) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.
Once running, the frequency and other parameters can be changed by programming the device using the I2C-bus connected between the Zynq module (master) and reference clock signal generator (slave).
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System Controller CPLD
The System Controller CPLD (U2) is central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For current CPLD Firmware description, check TE0745 CPLD
USB ULPI PHY
Hi-speed USB ULPI PHY (U32) is provided on the board. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U33).
MAC Address EEPROM
A serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use.
EEPROM
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Ethernet PHY
On-board Gigabit Ethernet PHY (U7) is provided on the board. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.
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LEDs
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Clock Sources
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Power and Power-On Sequence
Power Supply
Power supply with minimum current capability of 3.0 A for system startup is recommended.
Power Consumption
The maximum power consumption of a module mainly depends on the design which is running on the FPGA.
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* TBD - To Be Determined
For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.
| Warning |
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| To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
It is important that all baseboard I/Os are tri-stated at power-on until the "Power Good"-signals 'PWR_PS_OK' (J2-139) and 'PWR_PL_OK' (J2-135) are high, meaning that all on-module voltages have become stable and module is properly powered up.
Power Distribution Dependencies
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Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row). |
Power-On Sequence
The TE0745 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
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The Enable-Signal 'EN_PL' is permanently logic high in standard SC-CPLD firmware. The "Power Good"-signals 'PWR_PS_OK' and 'PWR_PL_OK' (latter low-active, extern pull-up needed) are available B2B-connector J2 (pins J2-139, J2-135) and on the SC-CPLD.
Voltage Monitor Circuit
The voltages 'VCCPINT' and 'PS_1.8V' are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (available on J2-131 or SC-CPLD) to GND. Leave this pin unconnected or connect to VDD (PS_1.8V) when unused.
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Power Rails
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Bank Voltages
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Board to Board Connectors
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Technical Specifications
Absolute Maximum Ratings
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Attention: PS_3.3V is directly connected to numerous on-board peripherals as supply and I/O voltage.
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Physical Dimensions
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
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Currently Offered Variants
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Set correct link to the shop page overview table of the product on English and German. Example for TE0728: ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0745-Zynq-SoC/ DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0745-Zynq-SoC/ if not available, set. |
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Revision History
Hardware Revision History
Product changes can be seen in TE0745 Product Change Notifications page.
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
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Table 16: LEDs of the module.
Power and Power-On Sequence
Power Consumption
The maximum power consumption of a module mainly depends on the design which is running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
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Power supply with minimum current capability of 3A for system startup is recommended.
For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.
| Warning |
|---|
| To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
It is important that all baseboard I/Os are tri-stated at power-on until the "Power Good"-signals 'PWR_PS_OK' (J2-139) and 'PWR_PL_OK' (J2-135) are high, meaning that all on-module voltages have become stable and module is properly powered up.
Power Distribution Dependencies
There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC converters, which power up further DCDC converters and the particular on-board voltages:
Figure 3: Power Distribution Diagram
See Xilinx data sheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0745 module.
| Note |
|---|
Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row). |
Power-On Sequence Diagram
The TE0745 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
Figure 4: Power-On Sequence
The Enable-Signal 'EN_PL' is permanently logic high in standard SC-CPLD firmware. The "Power Good"-signals 'PWR_PS_OK' and 'PWR_PL_OK' (latter low-active, extern pull-up needed) are available B2B-connector J2 (pins J2-139, J2-135) and on the SC-CPLD.
Voltage Monitor Circuit
The voltages 'VCCPINT' and 'PS_1.8V' are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (available on J2-131 or SC-CPLD) to GND. Leave this pin unconnected or connect to VDD (PS_1.8V) when unused.
Figure 5: Voltage monitor circuit.
Power Rails
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Voltages on B2B
Connectors
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B2B J1 Pin
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B2B J2 Pin
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Input/
Output
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147, 149, 151, 153,
155, 157, 159
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Table 18: Power rails of the SoC module on B2B connectors.
Bank Voltages
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Bank
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Voltage
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Voltage Range
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PL_1.8V, if R67 is equipped
PS_1.8V, if R68 is equipped
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Table 19: Range of SoC module's bank voltages.
B2B connectors
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Variants Currently In Production
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SoC Junction Temperature
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Table 20: Module variants.
Technical Specification
Absolute Maximum Ratings
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Parameter
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Units
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Notes
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3.3V nominal ± 5%
Attention: PS_3.3V is directly connected to numerous
on-board peripherals as supply and I/O voltage.
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PL IO bank supply voltage for HP I/O banks (VCCO)
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Voltage on module JTAG pins
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V
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Storage temperature
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-40
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+85
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°C
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Table 21: Module absolute maximum ratings.
| Note |
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| Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
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PL I/O bank supply voltage for HR
I/O banks (VCCO)
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PL I/O bank supply voltage for HP
I/O banks (VCCO)
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Xilinx datasheet DS191
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Table 22: Module recommended operating conditions.
| Note |
|---|
| Please check Xilinx datasheet DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Extended grade: 0°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Physical Dimensions
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
All dimensions are given in millimeters.
Figure 6: Physical dimensions of the TE0745 SoC module.
Revision History
Hardware Revision History
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Notes
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- First Production release
Refer to Changes list in Schematic for
further details in changes to REV01
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- Prototypes
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Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Figure 7: TE0745 module revision number.
Document Change History
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Revision
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- add power note
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