Versions Compared

Old Version 13

changes.mady.by.user Ali Naseri

Saved on

compared with

New Version 14

changes.mady.by.user Ali Naseri

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Interface on B2B connectors
 

 

The B2B connector provides further interfaces like 'JTAG' and 'I²C' to the System Controller CPLD:

InterfacesI/O signal countpin schematic names / B2B pinsconnected withNotes
JTAG5

TMS, pin J1-144

TDI, pin J1-142

TDO, pin J1-145

TCK, pin J1-143

 JTAG_EN, pin J1-148

SC CPLD, bank 0
Note
JTAG_EN pin in B2B connector J1-148 should be kept low or grounded for normal operation!

At normal operation the JTAG-signals will be forwarded to the SoC module. Else the JTAG_EN pin must be high or open to update the CPLD firmware via JTAG-interface.

VCCIO: PS_3.3V

I²C2

I2C_33_SCL, pin J2-119

I2C_33_SDA, pin J2-121

RTC, U24

SC CPLD, U2

MAC Address EEPROM, U23

Zynq-module, U1

Quad programmable PLL clock generator, U16


The I²C-interface of the RTC U24 (pin 12: SCL, pin 11: SDA) and the B2B-connector J2 are operating with the reference voltage PS_3.3V.

Following component's I²C-interfaces are operating with the reference voltage PS_1.8V (voltage level shifting

(

3.3V ↔ 1.8V

)

via I²C bus repeater U17):

SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL)

MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA)

Zynq-chip U1, bank 500 (MIO0), pins A25 (SCL), B26 (SDA)

Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA)

Component's I²C Addresses:

RTC: 0x6F

RTC RAM: 0x57

MAC Address EEPROM: 0x53

Quad programmable PLL clock generator: 0x70

control lines5RST_IN_N, pin J2-131

PS_SRST, pin J2-152

BOOTMODE, pin J2-133

PWR_PL_OK, pin J2-135
PWR_PS_OK, pin J2-139
SC CPLD bank 0, pins 25; Reset Circuit U41, pin 3

SC CPLD bank 2, pin 12; Zynq-chip bank 501, pin A22

Zynq-chip bank 500, pin F24
SC CPLD bank 0, pin 27; PG-signal DCDC-converter U8, pin 9

SC CPLD bank 0, pin 28; PG-signal DCDC-converter U31, pin 2

Low-active Power-On reset-pin, controls POR_B-signal (bank 500, pin C23) of Zynq-chip.
PS_SRST, pin J2-152SC CPLD bank 2, pin 12; Zynq-chip bank 501, pin A22Low-active system-reset pin
Low-active Power-On reset-pin, controls POR_B-signal (bank 500, pin C23)
of Zynq-chip.
Low-active system-reset pin of
BOOTMODE, pin J2-133Zynq-chip
.
bank 500, pin F24Control line which sets in conjunction with signal 'BOOTMODE1' the boot source of the Zynq-chip. See section "Boot Modes".
PWR_PL_OK, pin J2-135SC CPLD bank 0, pin 27; PG-signal DCDC-converter U8, pin 9Indicates stable state of PL supply voltage (low-active).
PWR_PS_OK, pin J2-139SC CPLD bank 0, pin 28; PG-signal DCDC-converter U31, pin 2Indicates stable state of PS supply voltage (low-active).

Table 4:  B2B connector pin-outs of available interfaces

System Controller

...

CPLD

Special purpose pins are connected to System Controller CPLD and have following default configuration:

...