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The B2B connector provides further interfaces like 'JTAG' and 'I²C' to the System Controller CPLD:

InterfacesI/O signal countpin schematic names / B2B pinsconnected withNotes
JTAG5

TMS, pin J1-144

TDI, pin J1-142

TDO, pin J1-145

TCK, pin J1-143

 JTAG_EN, pin J1-148

SC CPLD, bank 0
Note
JTAG_EN pin in B2B connector J1-148 should be kept low or grounded for normal operation!

At normal operation the JTAG-signals will be forwarded to the SoC module. Else the JTAG_EN pin must be high or open to update the CPLD firmware via JTAG-interface.

VCCIO: PS_3.3V

I²C2

I2C_33_SCL, pin J2-119

I2C_33_SDA, pin J2-121

RTC, U24

SC CPLD, U2

MAC Address EEPROM, U23

Zynq-module, U1

Quad programmable PLL clock generator, U16


The I²C-interface of the RTC U24 (pin 12: SCL, pin 11: SDA) and the B2B-connector J2 are operating with the reference voltage PS_3.3V.

Following component's I²C-interfaces are operating with the reference voltage PS_1.8V (voltage level shifting 3.3V ↔ 1.8V via I²C bus repeater U17):

SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL)

MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA)

Zynq-chip U1, bank 500 (MIO0), pins A25 (SCL), B26 (SDA)

Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA)

Component's I²C Addresses:

RTC: 0x6F

RTC RAM: 0x57

MAC Address EEPROM: 0x53

Quad programmable PLL clock generator: 0x70

control lines5RST_IN_N, pin J2-131SC CPLD bank 0, pins 25; Reset Circuit U41, pin 3Low-active Power-On reset
-
pin, controls POR_B-signal (bank 500, pin C23) of Zynq-chip.
PS_SRST, pin J2-152SC CPLD bank 2, pin 12; Zynq-chip bank 501, pin A22Low-active system-reset pin of Zynq-chip.
BOOTMODE, pin J2-133Zynq-chip bank 500, pin F24Control line which sets in conjunction with signal 'BOOTMODE1' the boot source of the Zynq-chip. See section "Boot Modes".
PWR_PL_OK, pin J2-135SC CPLD bank 0, pin 27; PG-signal DCDC-converter U8, pin 9Indicates stable state of PL supply voltage (low-active) after power-up sequence.
PWR_PS_OK, pin J2-139SC CPLD bank 0, pin 28; PG-signal DCDC-converter U31, pin 2Indicates stable state of PS supply voltage (low-active) after power-up sequence.

Table 4:  B2B connector pin-outs of available interfaces

System Controller CPLD

Special purpose pins are connected to System Controller CPLD and have following default configuration:

...

No hard wired function on PCB, when forced low pulls POR_B low to

emulate power on reset.

...

Active low reset, gated to POR_B.

...

LEDs

...

D2

...

Green

...

DONE

...

Reflects inverted DONE signal. ON when FPGA is not configured,

OFF as soon as PL is configured.

This LED will not operate if the SC can not power on the 3.3V output

rail that also powers the 3.3V circuitry on the module.

...

D3

...

Red

...

SC

...

D4

...

Green

...

MIO7

...

User controlled, default OFF (when PS7 has not been booted).

Default MIO Mapping

MIOFunctionconnected withNotes MIOFunctionconnected withNotes
0GPIOJ2-137, SC CPLD bank 2, pin 14user I/O on B2B 16..27ETH0Ethernet PHY U7RGMII
1QSPI0QSPI Flash Memory U14, pin C2SPI Flash-CS 28..39USB0USB PHY U32ULPI
2QSPI0QSPI Flash Memory U14, pin D3SPI Flash-DQ0 40GPIOJ2-150user I/O on B2B
3QSPI0QSPI Flash Memory U14, pin D2SPI Flash-DQ1 41GPIOJ2-152user I/O on B2B
4QSPI0QSPI Flash Memory U14, pin C4SPI Flash-DQ2 42GPIOJ2-154user I/O on B2B
5QSPI0QSPI Flash Memory U14, pin D4SPI Flash-DQ3 43GPIOJ2-156user I/O on B2B
6QSPI0QSPI Flash Memory U14, pin B2SPI Flash-SCK 44GPIOJ2-158user I/O on B2B
7GPIOUSB PHY U32, pin 27USB PHY Reset 45GPIOJ2-160user I/O on B2B
8GPIOSC CPLD bank 2, pin 13user I/O 46GPIOJ2-145

user I/O on B2B

9GPIOEthernet PHY U7, pin 16Ethernet PHY Reset 47GPIOJ2-147user I/O on B2B
10I²C SCL-line I²C-interface1.8V ref. voltage 48GPIOJ2-149user I/O on B2B
11I²C SDA-line I²C-interface1.8V ref. voltage 49GPIOJ2-151user I/O on B2B
12GPIOJ2-123user I/O on B2B 50GPIOJ2-153user I/O on B2B
13GPIOJ2-125user I/O on B2B 51GPIOJ2-155user I/O on B2B
14GPIOJ2-127user I/O on B2B 52ETH0USB PHY U32, pin 7MDC
15GPIOJ2-129user I/O on B2B 53ETH0USB PHY U32, pin 8MDIO

Table 5: Default MIO Mapping

Gigabit Ethernet Interface

On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U9), the 125MHz output clock is available on B2B connector J2, pin J2-150.

PHY PinZYNQ PSB2BNotes
MDC/MDIOMIO52, MIO53--
PHY LEDs-

PHY_LED0: J2-144
PHY_LED1: J2-146

-
PHY_LED2 / INTn:-J2-148low active interrupt line
PHY_CLK125M-J2-150125 MHz Ethernet PHY clock out
CONFIG--permanent high (PS_1.8V)
RESETnMIO9-low active reset line
RGMIIMIO16..MIO27-Reduced Gigabit Media Independent Interface
SGMII--Serial Gigabit Media Independent Interface
MDI-PHY_MDI0: J2-120 / J2-122
PHY_MDI1: J2-126 / J2-128
PHY_MDI2: J2-132 / J2-134
PHY_MDI3: J2-138 / J2-140		Media Independent Interface

Table 6: Ethernet PHY interface connections

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.

Default MIO Mapping

...

Ethernet PHY LED2

INTn Signal.

...

Gigabit Ethernet

On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz 25 MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).U15).

USB Ethernet PHY connection

MIO52, MIO53
PHY PinZYNQ PSPinZYNQ PLB2B NameNotesMDC/MDIO
ULPIMIO28..39-Zynq USB0 MIO pins are connected to the PHY.
REFCLK-LED0-J3Can be routed via PL to any free PL I/O pin in B2B connector.
LED1-K8

Can be routed via PL to any free PL I/O pin in B2B connector.

This LED is connected to PL via level-shifter implemented in

system controller CPLD.

LED2/InterruptMIO46--
CONFIG--

By default the PHY address is strapped to 0x00, alternate

configuration is possible.

RESETnMIO50--
RGMIIMIO16..MIO27--
SGMII--on B2B.
MDI--on B2B.

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 25 MHz oscillator (U15).

USB PHY connection

...

-52MHz from on board oscillator (U15).
REFSEL[0..2]--Reference clock frequency select, all set to GND selects 52MHz.
RESETBMIO51-Active low reset.
CLKOUTMIO36-Connected to 1.8V, selects reference clock operation mode.
DP, DM-OTG_D_P, OTG_D_NUSB data lines.
CPEN-VBUS_V_ENExternal USB power switch active high enable signal.
VBUS-USB_VBUSConnect to USB VBUS via a series of resistors, see reference schematics.
ID-OTG_IDFor an A-Device connect to ground, for a B-Device left floating.

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

MAC Address EEPROM

A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the main board. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.

LEDs

LEDColorConnected toDescription and Notes

D1

Green

DONE

Reflects inverted DONE signal. ON when FPGA is not configured,

OFF as soon as PL is configured.

This LED will not operate if the SC can not power on the 3.3V output

rail that also powers the 3.3V circuitry on the module.

D2

Red

SC

System main status LED.

 

Boot Modes

By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.

 MODE Signal StateBoot Mode

High or open

QSPI

Low or ground

SD Card

System Controller CPLD

Special purpose pins are connected to System Controller CPLD and have following default configuration:

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

Boot Modes

By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.

...

MODE Signal State

...

High or open

...

QSPI

...

Low or ground

...

SD Card

On-board Peripherals

Processing System (PS) Peripherals

...

Temperature compensated RTC.

...

Clocking

ClockFrequencyICFPGANotes

PS CLK

33.3333 MHz

U11

PS_CLK

PS subsystem main clock.

ETH PHY reference

25 MHz

U9

-

-

USB PHY reference

52 MHz

U15

-

-

PLL reference

25 MHz

U18

-

-

GT REFCLK0

-

B2B

U9/V9

Externally supplied from baseboard.

GT REFCLK1

125 MHz

U10 Si5338

U5/V5

Default clock is 125 MHz.

RTC - Real Time Clock

clock is 125 MHz.

 An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the main board. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.

PLL - Phase-Locked Loop

There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.

...

I/ODefault FrequencyNotes

IN1/IN2

Externally supplied

Needs decoupling on base board.

IN3

25MHz

Fixed input clock.

IN4

-

-

IN5/IN6

125MHz

Ethernet PHY output clock.

CLK0

-

Not used, disabled.

CLK1

-

Not used, disabled.

CLK2 A/B

125MHz

MGT reference clock 1.

CLK3A

- 

Bank 34 clock input, default disabled, User clock.

CLK3B

-

Not used, disabled.

MAC Address EEPROM

A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.

board.

IN3

25MHz

Fixed input clock.

IN4

-

-

IN5/IN6

125MHz

Ethernet PHY output clock.

CLK0

-

Not used, disabled.

CLK1

-

Not used, disabled.

CLK2 A/B

125MHz

MGT reference clock 1.

CLK3A

- 

Bank 34 clock input, default disabled, User clock.

CLK3B

-

Not used, disabled.

 

Power and Power-On Sequence

...

See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.

page-break 

Power Rails

Voltages on B2B

Connectors

B2B JM1 Pin

B2B JM2-Pin

Input/

Output

Note
VIN1, 3, 52, 4, 6, 8InputSupply voltage.
3.3VIN13, 15-InputSupply voltage.
VCCIO139, 11-InputHigh range bank voltage.
VCCIO34-5Input

TE0715-xx-15: high range bank voltage.

TE0715-xx-30: high performance bank voltage.
VCCIO35-7, 9Input

TE0715-xx-15: high range bank voltage.

TE0715-xx-30: high performance bank voltage.
VBAT_IN79-InputRTC battery-buffer supply voltage.
3.3V-10, 12OutputInternal 3.3V voltage level.
1.8V39-OutputInternal 1.8V voltage level.
DDR_PWR-19OutputInternal 1.5V or 1.35V voltage level, depends on revision.
VREF_JTAG 91OutputJTAG reference voltage (3.3V).

...

Bank          

Schematic Name

Voltage

TE0715-xx-15        

TE0715-xx-30           

500VCCO_MIO0_500  3.3V--
501VCCO_MIO1_501  1.8V--
502VCCO_DDR_502   1.5V--
0 ConfigVCCO_03.3V--
13 HRVCCO_13UserHR: 1.2V to 3.3V
HR: 1.2V to 3.3V
34 HR/HPVCCO_34UserHR: 1.2V to 3.3V
HP: 1.2V to 1.8V
35 HR/HPVCCO_35UserHR: 1.2V to 3.3V
HP: 1.2V to 1.8V

...

B2B connectors

Include Page
IN:SS5-ST5 connectors
IN:SS5-ST5 connectors

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Notes

VIN supply voltage

-0.3

6.0

V

-

3.3VIN supply voltage

-0.4

3.6

V

-
VBAT supply voltage-16.0V-
PL IO bank supply voltage for HR I/O banks (VCCO)-0.53.6V-

PL IO bank supply voltage for HP I/O banks (VCCO)

-0.52.0VTE0715-xx-15 does not have HP banks.
I/O input voltage for HR I/O banks-0.4VCCO_X+0.55V-
I/O input voltage for HP I/O banks-0.55VCCO_X+0.55VTE0715-xx-15 does not have HP banks.
GT receiver (RXP/RXN) and transmitter (TXP/TXN)-0.51.26V-

Voltage on module JTAG pins

-0.4

VCCO_0+0.55

V

VCCO_0 is 3.3V nominal.

Storage temperature

-40

+85

°C

-
Storage temperature without the ISL12020MIRZ-55+100°C-

...

ParameterMinMaxUnitsNotesReference Document
VIN supply voltage2.55.5V  
3.3VIN supply voltage3.1353.465V  
VBAT_IN supply voltage2.75.5V  

PL I/O bank supply voltage for HR

I/O banks (VCCO)

1.143.465V Xilinx datasheet DS191

PL I/O bank supply voltage for HP

I/O banks (VCCO)

1.141.89V

TE0715-xx-15 does not have

HP banks

Xilinx datasheet DS191
I/O input voltage for HR I/O banks(*)(*)V(*) Check datasheet

Xilinx datasheet DS191

or DS187

I/O input voltage for HP I/O banks(*)(*)V

TE0715-xx-15 does not have

HP banks

(*) Check datasheet

Xilinx datasheet DS191
Voltage on Module JTAG pins3.1353.465VVCCO_0 is 3.3 V nominal 

B2B connectors

...

Absolute Maximum Ratings

Recommended Operating Conditions

...