Page History
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- Xilinx Zynq XC7Z family SoC, U1
- 256 Mbit Quad SPI Flash memory Micron N25Q256A, U12
- Reference clock signal oscillator SiTime SiT8008BI @33.333333 MHz, U12
- Reference clock signal oscillator SiTime SiT8008BI @25.000000 MHz, U9
- Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16-bit word width), U3
- TI TPS51206 DDR3 memory termination regulator with buffered reference voltage VTTREF, U18
- Intersil ISL12020MIRZ Real-Time-Clock, U24
- TI TCA9517 level-shifting I2C bus repeater, U17
- Red LED, D2
- Green LED, D1
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 banks a 32 MWords, 16 Bit Word-Widthword width), U5
- Altera Enpirion EN63A0QI 12A DC-DC PowerSoC @1.0V (VCCINT), U4
- TI TPS74401RGW LDO DC-DC regulator @1.2V (MGTAVTT), U8
- TI TPS72018DRVR LDO DC-DC regulator @1.8V (MGTAUX), U6
- TI TPS74401RGW LDO DC-DC regulator @1.0V (MGTAVCC), U11
- Silicon Labs Si5338A I2C Programmable Quad Clock Generator, U13
- Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
- 256 Mbit Quad SPI Flash memory (Micron N25Q256A, U14
- Microchip USB3320 USB transceiver PHY , U32
- Reference clock signal oscillator SiTime SiT8008BI @52.000000 MHz, U33
- Microchip 24AA025E48 EEPROM for MAC address, U23
- Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
Initial Delivery State
Storage device nameDevice Name | Content | Notes |
|---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC Address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
| Si5338 OTP NVM | Default settings pre programmed | OTP not re-programmable after delivery from factory |
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The configuration of the I/O's MIO12 - MIO15 and MIO40 - MIO51 are depending on the base-board peripherals connected to this these pins.
| MIO | Function | Connected to | Notes | MIO | Function | Connected to | Notes | |
|---|---|---|---|---|---|---|---|---|
| 0 | GPIO | J2-137, SC CPLD bank 2, pin 14 | User configurable I/O on B2B. | 16..27 | ETH0 | Ethernet PHY U7 | RGMII | |
| 1 | QSPI0 | QSPI Flash Memory U14, pin C2 | SPI Flash-CS | 28..39 | USB0 | USB PHY U32 | ULPI | |
| 2 | QSPI0 | QSPI Flash Memory U14, pin D3 | SPI Flash-DQ0 | 40 | - | J2-150 | User configurable I/O on B2B. | |
| 3 | QSPI0 | QSPI Flash Memory U14, pin D2 | SPI Flash-DQ1 | 41 | - | J2-152 | User configurable I/O on B2B. | |
| 4 | QSPI0 | QSPI Flash Memory U14, pin C4 | SPI Flash-DQ2 | 42 | - | J2-154 | User configurable I/O on B2B. | |
| 5 | QSPI0 | QSPI Flash Memory U14, pin D4 | SPI Flash-DQ3 | 43 | - | J2-156 | User configurable I/O on B2B. | |
| 6 | QSPI0 | QSPI Flash Memory U14, pin B2 | SPI Flash-SCK | 44 | - | J2-158 | User configurable I/O on B2B. | |
| 7 | GPIO | USB PHY U32, pin 27 | Low active USB PHY Reset (pulled-up to PS_1.8V) | 45 | - | J2-160 | User configurable I/O on B2B. | |
| 8 | GPIO | SC CPLD bank 2, pin 13 | User I/O (pulled-up to PS_1.8V) | 46 | - | J2-145 | User configurable I/O on B2B. | |
| 9 | GPIO | Ethernet PHY U7, pin 16 | Ethernet PHY Reset | 47 | - | J2-147 | User configurable I/O on B2B. | |
| 10 | I²C | SCL line I2C-interface | 1.8V ref. voltage | 48 | - | J2-149 | User configurable I/O on B2B. | |
| 11 | I²C | SDA line I2C-interface | 1.8V ref. voltage | 49 | - | J2-151 | User configurable I/O on B2B. | |
| 12 | - | J2-123 | User configurable I/O on B2B. | 50 | - | J2-153 | User configurable I/O on B2B. | |
| 13 | - | J2-125 | User configurable I/O on B2B. | 51 | - | J2-155 | User configurable I/O on B2B. | |
| 14 | - | J2-127 | User configurable I/O on B2B. | 52 | ETH0 | USB PHY U32, pin 7 | MDC | |
| 15 | - | J2-129 | User configurable I/O on B2B. | 53 | ETH0 | USB PHY U32, pin 8 | MDIO |
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| Name | IC | ID | PS7 | MIO | Notes |
|---|---|---|---|---|---|
| SPI Flash | S25FL256SAGBHI20 | U14 | QSPI0 | MIO1..MIO6- | 32 MByte Flash memory at standard configuration |
MAC Address EEPROM
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
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Overview
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