Page History
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The B2B connectors are high-speed hermaphroditic stacking strips providing modular interface to the SoC's PL and PS I/Os. Both single ended and differential signalling signaling LVDS pairs are supported.
| Bank | Type | B2B Connector | I/O SignalsSignal Count | LVDS Pairs Count | Bank Voltage | Notes |
|---|---|---|---|---|---|---|
| 12 | HR | J1 | 50 | 24 | VCCIO_12 pins J1-54, J1-55 | Voltage range 1.2V to 3.3V |
| 13 | HR | J1 | 50 | 24 | VCCIO_13 pins J1-112, J1-113 | Voltage range 1.2V to 3.3V |
| 33 | HP | J3 | 50 | 24 | VCCIO_33 pins J3-115, J3-120 | Voltage range 1.2V to 1.8V |
| 34 | HP | J2 | 50 | 24 | VCCIO_34 pins J2-29, J2-30 | Voltage range 1.2V to 1.8V |
| 35 | HP | J2 | 50 | 24 | VCCIO_35 pins J2-87, J2-88 | Voltage range 1.2V to 1.8V |
| 500 | MIO | J2 | 5 | - | 1.8V | MIO0, MIO12 ... MIO15, user configurable I/O's on B2B |
| 501 | MIO | J3 | 12 | - | 1.8V | MIO40 ... MIO51, user configurable I/O's on B2B |
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| Bank | Type | Lane Count | B2B Connector | Schematics Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs (LVDS pairs) |
|---|---|---|---|---|---|
| 111 | GTX | 4 | J1 | MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21 MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15 MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9 MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5 | 1 Reference clock MGT_CLK3 from programmable 1 Reference clock MGT_CLK2 from B2B connector J3 |
| 112 | GTX | 4 | J3 | MGT_RX3_P, MGT_RX3_N, pins J3-68, J3-70 MGT_RX2_P, MGT_RX2_N, pins J3-62, J3-64 MGT_RX1_P, MGT_RX1_N, pins J3-56, J3-58 MGT_RX0_P, MGT_RX0_N, pins J3-50, J3-52 | 1 Reference clock MGT_CLK1 from programmable 1 Reference clock MGT_CLK0 from B2B connector J3 |
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| Note |
|---|
| JTAG_EN pin 148 in B2B connector J1 should be kept low or grounded for normal operation! |
System Controller I/O
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Following special purpose pins are connected to System Controller CPLD:
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The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals can be are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
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Power and Power-On Sequence
Power
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Consumption
The maximum power consumption of a module mainly depends on the design which is running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
| Power Input Pin | Typical Current |
|---|---|
| PL_VIN | TBD* |
| PS |
Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption
| Power Input Pin | Typical Current |
|---|---|
| PL_VIN | TBD* |
| PS_VIN | TBD* |
| PS_3.3V | TBD* |
Table 15: Maximum current of power supplies. *to be determined soon with reference design setup.
Power supply with minimum current capability of 3A for system startup is recommended.
For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
Power-On Sequence
The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.
| Warning |
|---|
| To avoid any damage to the SoC module, check for stabilized on-board voltages in steady state before powering up the SoC's I/O bank voltages VCCO_x. All I/O's should be tri-stated during power-on sequence. |
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
It is important that all baseboard I/Os are 3are tri-stated at power-on until the "Power Good"-signals 'PWR_PS_OK' (J2-139) and 'PWR_PL_OK' (J2-135) are high, meaning that all on-module voltages have become stable and module is properly powered up.
Power Distribution Dependencies
There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC converters, which power up further DCDC converters and the particular on-board voltages:
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| Parameter | Min | Max | Units | Notes | Reference Document |
|---|---|---|---|---|---|
| PL_VIN | 3.3 | 4.5 | V | - | TI TPS720 data sheet |
| PS_VIN | 3.3 | 6.0 | V | - | TI TPS82085 data sheet |
| PS_3.3V | 3.135 | 3.465 | V | - | 3.3V nominal ± 5% |
| VBAT_IN supply voltage | 2.7 | 5.5 | V | - | ISL12020MIRZ data sheet |
PL I/O bank supply voltage for HR | 1.14 | 3.465 | V | - | Xilinx datasheet DS191 |
PL I/O bank supply voltage for HP | 1.14 | 1.89 | V | - | Xilinx datasheet DS191 |
| I/O input voltage for HR I/O banks | -0.20 | VCCO_X+0.20 | V | - | Xilinx datasheet DS191 |
| I/O input voltage for HP I/O banks | -0.20 | VCCO_X+0.20 | V | - | Xilinx datasheet DS191 |
| GT receiver (RXP/RXN) and transmitter (TXP/TXN) | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 |
| Voltage on Module JTAG pins | 3.135 | 3.6 | V | JTAG signals forwarded to Zynq module config bank 0 | MachX02 Family Data Sheet |
| Note |
|---|
| Please check Xilinx datasheet DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
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Industrial grade: -40°C to +85°C.
Extended grade: 0°C to +85°C.
The module Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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Physical Dimensions
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
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Figure 4: Physical dimensions of the TE0745 SoC module
Weight
24 g - Plain module
Revision History
Hardware Revision History
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| Date | Revision | Contributors | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Ali Naseri, Jan Kumann | First TRM release. | |||||||||||
| 2017-02-05 | V1
| Jan Kumann | Initial document. |
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