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PS MIO Configuration
| MIO | Interface |
|---|
| MIO 0...12 | QSPI Flash Memory |
| MIO 20...21 | I2C 1 |
| MIO 22...23 | UART 0 |
| MIO 26...37 | GEM 0 |
| MIO 46...51 | SD 1 |
| MIO 52...63 | USB 0 |
| MIO 64...75 | USB 1 |
| MIO 76...77 | MDIO 0 |
DDR4 SODIMM Socket
The Zynq UltraScale+ DDRC hard memory controller is wired to the DDR4 SODIMM Socket U3.
Quad-SPI Flash Memory
Board has two N25Q512A11G1240E connected in a dual parallel mode.
I2C
The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.
| I2C address | Chip | Description |
|---|
| 0x50 | U63 24AA128T-I/ST | 128K Serial EEPROM |
| 0x53 | U64 24AA025E48T-I/OT | 2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity |
| 0x69 | U14 Si5345 | Clock generator and distributor |
UART and JTAG
Board has USB-UART bridge based on FTDI FT2232 chip. Use of this feature requires that USB driver is installed on your host PC. UART0 with MIO 22 .. 23 should be selected in "Zynq UltraScale+ MPSoC" configuration.
The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.
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Ethernet
SD
USB
DACs
MGT
Clocking
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Power supply
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